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esp32.rs (3173B)

      1 const SOC_MMU_VADDR_MASK: u32 = 0x3FFFFF;
      2 const SOC_MMU_INVALID: u32 = 1 << 8;
      3 const MMU_LL_PSRAM_ENTRY_START_ID: u32 = 1152;
      4 const SOC_IRAM0_CACHE_ADDRESS_LOW: u32 = 0x400D0000;
      5 const SOC_IRAM0_CACHE_ADDRESS_HIGH: u32 = 0x40400000;
      6 const SOC_IRAM1_CACHE_ADDRESS_LOW: u32 = 0x40400000;
      7 const SOC_IRAM1_CACHE_ADDRESS_HIGH: u32 = 0x40800000;
      8 const SOC_IROM0_CACHE_ADDRESS_LOW: u32 = 0x40800000;
      9 const SOC_IROM0_CACHE_ADDRESS_HIGH: u32 = 0x40C00000;
     10 const SOC_DRAM1_CACHE_ADDRESS_LOW: u32 = 0x3F800000;
     11 const SOC_DRAM1_CACHE_ADDRESS_HIGH: u32 = 0x3FC00000;
     12 const SOC_DROM0_CACHE_ADDRESS_LOW: u32 = 0x3F400000;
     13 const SOC_DROM0_CACHE_ADDRESS_HIGH: u32 = 0x3F800000;
     14 const DPORT_PRO_FLASH_MMU_TABLE: u32 = 0x3FF10000;
     15 
     16 pub fn mmu_ll_get_page_size(_mmu_id: u32) -> u32 {
     17     crate::mmu_hal::MMU_PAGE_64KB
     18 }
     19 
     20 pub fn mmu_ll_get_entry_id(_mmu_id: u32, vaddr: u32) -> u32 {
     21     let mut offset = 0;
     22     let mut shift_code = 0;
     23     let mut vaddr_mask = 0;
     24 
     25     if soc_address_in_bus!(SOC_DROM0_CACHE, vaddr) {
     26         offset = 0;
     27         shift_code = 16;
     28         vaddr_mask = SOC_MMU_VADDR_MASK;
     29     } else if soc_address_in_bus!(SOC_IRAM0_CACHE, vaddr) {
     30         offset = 64;
     31         shift_code = 16;
     32         vaddr_mask = SOC_MMU_VADDR_MASK;
     33     } else if soc_address_in_bus!(SOC_IRAM1_CACHE, vaddr) {
     34         offset = 128;
     35         shift_code = 16;
     36         vaddr_mask = SOC_MMU_VADDR_MASK;
     37     } else if soc_address_in_bus!(SOC_IROM0_CACHE, vaddr) {
     38         offset = 192;
     39         shift_code = 16;
     40         vaddr_mask = SOC_MMU_VADDR_MASK;
     41     } else if soc_address_in_bus!(SOC_DRAM1_CACHE, vaddr) {
     42         offset = MMU_LL_PSRAM_ENTRY_START_ID;
     43         shift_code = 15;
     44         vaddr_mask = SOC_MMU_VADDR_MASK >> 1;
     45     } else {
     46         error!("mmu_ll_get_entry_id failed!");
     47     }
     48 
     49     offset + ((vaddr & vaddr_mask) >> shift_code)
     50 }
     51 
     52 pub fn mmu_ll_entry_id_to_paddr_base(_mmu_id: u32, entry_id: u32) -> u32 {
     53     let level = unsafe { dport_interrupt_disable() };
     54     let mmu_val = unsafe { *(DPORT_PRO_FLASH_MMU_TABLE as *const u32).offset(entry_id as isize) };
     55     unsafe { dport_interrupt_restore(level) };
     56 
     57     if entry_id >= MMU_LL_PSRAM_ENTRY_START_ID {
     58         mmu_val << 15
     59     } else {
     60         mmu_val << 16
     61     }
     62 }
     63 
     64 pub fn mmu_ll_check_entry_valid(_mmu_id: u32, entry_id: u32) -> bool {
     65     let level = unsafe { dport_interrupt_disable() };
     66     let mmu_val = unsafe { *(DPORT_PRO_FLASH_MMU_TABLE as *const u32).offset(entry_id as isize) };
     67     unsafe { dport_interrupt_restore(level) };
     68 
     69     (mmu_val & SOC_MMU_INVALID) == 0
     70 }
     71 
     72 // NOTE:Idk if required!
     73 // Only used when using second core etc.
     74 
     75 const SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL: u32 = 5;
     76 #[inline(always)]
     77 unsafe fn dport_interrupt_disable() -> u32 {
     78     let level: u32;
     79 
     80     unsafe {
     81         core::arch::asm!(
     82             "rsil {0}, {1}",
     83             out(reg) level,
     84             const SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL,
     85             options(nomem, nostack)
     86         );
     87     }
     88 
     89     level
     90 }
     91 
     92 #[inline(always)]
     93 unsafe fn dport_interrupt_restore(level: u32) {
     94     unsafe {
     95         core::arch::asm!(
     96             "wsr.ps {0}; rsync",
     97             in(reg) level,
     98             options(nomem, nostack)
     99         );
    100     }
    101 }