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esp32c2.rs (1604B)

      1 use crate::mmu_hal::{MMU_PAGE_16KB, MMU_PAGE_32KB, MMU_PAGE_64KB};
      2 
      3 const DR_REG_MMU_TABLE: u32 = 0x600c5000;
      4 const SOC_MMU_VALID_VAL_MASK: u32 = 0x3f;
      5 const SOC_MMU_INVALID: u32 = 1 << 6;
      6 
      7 fn soc_mmu_vaddr_mask(mmu_id: u32) -> u32 {
      8     mmu_ll_get_page_size(mmu_id) * 64 - 1
      9 }
     10 
     11 pub fn mmu_ll_get_page_size(_mmu_id: u32) -> u32 {
     12     let extmem = unsafe { &*esp32c2::EXTMEM::ptr() };
     13     let cache_mmu_page_size = extmem.cache_conf_misc().read().cache_mmu_page_size().bits();
     14     match cache_mmu_page_size {
     15         0 => MMU_PAGE_16KB,
     16         1 => MMU_PAGE_32KB,
     17         _ => MMU_PAGE_64KB,
     18     }
     19 }
     20 
     21 pub fn mmu_ll_get_entry_id(mmu_id: u32, vaddr: u32) -> u32 {
     22     let shift_code = match mmu_ll_get_page_size(mmu_id) {
     23         MMU_PAGE_64KB => 16,
     24         MMU_PAGE_32KB => 15,
     25         MMU_PAGE_16KB => 14,
     26         _ => {
     27             error!("mmu_ll_get_entry_id failed!");
     28 
     29             0
     30         }
     31     };
     32 
     33     (vaddr & soc_mmu_vaddr_mask(mmu_id)) >> shift_code
     34 }
     35 
     36 pub fn mmu_ll_entry_id_to_paddr_base(mmu_id: u32, entry_id: u32) -> u32 {
     37     let shift_code = match mmu_ll_get_page_size(mmu_id) {
     38         MMU_PAGE_64KB => 16,
     39         MMU_PAGE_32KB => 15,
     40         MMU_PAGE_16KB => 14,
     41         _ => {
     42             error!("mmu_ll_entry_id_to_paddr_base failed!");
     43 
     44             0
     45         }
     46     };
     47 
     48     let ptr = (DR_REG_MMU_TABLE + entry_id * 4) as *const u32;
     49     unsafe { ((*ptr) & SOC_MMU_VALID_VAL_MASK) << shift_code }
     50 }
     51 
     52 pub fn mmu_ll_check_entry_valid(_mmu_id: u32, entry_id: u32) -> bool {
     53     let ptr = (DR_REG_MMU_TABLE + entry_id * 4) as *const u32;
     54     unsafe { ((*ptr) & SOC_MMU_INVALID) == 0 }
     55 }