default.nix (26336B)
1 { 2 description = '' 3 4 == OpenWrt One 5 6 === Hardware summary 7 8 * MediaTek MT7981B (1300MHz) 9 * 256MB NAND Flash 10 * 1024MB RAM 11 * WLan hardware: Mediatek MT7976C 12 13 === Status 14 15 * Only tested over TFTP so far. 16 * WiFi (2.4G and 5G) works. 17 * 2.5G ethernet port works. 18 19 === Limitations 20 21 * adding `he_bss_color="128"` causes `Invalid argument` for hostap 22 * nvme support untested 23 * I don't think the front LEDs work yet 24 25 === Installation 26 27 TODO: add instructions on how to boot directly from TFTP to memory and 28 how to install from TFTP to flash without going through OpenWrt. 29 30 The instructions below assume you can boot and SSH into OpenWrt, for 31 example by attaching a USB serial console to the front port, selecting 32 'boot from recovery' in the U-Boot menu, and connecting to 33 root@192.168.1.1 via the 1G ethernet port. 34 35 Boot into OpenWrt and create a 'liminix' UBI partition: 36 37 [source,console] 38 ---- 39 root@OpenWrt:~# ubimkvol /dev/ubi0 --name=liminix --maxavsize 40 ---- 41 42 Remember the 'Volume ID' that was created for this new partition, or 43 find the one labeled 'liminix' using 'ubinfo -d 0 -n 5' etc. 44 45 Build the UBI image and write it to this new partition: 46 47 48 [source,console] 49 ---- 50 $ nix-build -I liminix-config=./my-configuration.nix --arg device 51 "import ./devices/openwrt-one" -A outputs.default 52 $ cat result/rootfs | ssh root@192.168.1.1 "cat > /tmp/rootfs" 53 $ ssh root@192.168.1.1 54 root@OpenWrt:~# ubiupdatevol /dev/ubi0_X /tmp/rootfs # replace X 55 with the volume id, if needed check with `ubinfo` 56 ---- 57 58 Reboot into the U-Boot prompt and boot with: 59 60 [source,console] 61 ---- 62 OpenWrt One> ubifsmount ubi0:liminix && ubifsload ''${loadaddr} boot/fit && bootm ''${loadaddr} 63 ---- 64 65 If this works, reboot into OpenWrt and configure U-Boot to boot ubifs by 66 default: 67 68 [source,console] 69 ---- 70 root@OpenWrt:~# fw_setenv orig_boot_production $(fw_printenv -n boot_production) 71 root@OpenWrt:~# fw_setenv boot_production 'led white on ; ubifsmount ubi0:liminix && ubifsload ''${loadaddr} boot/fit && bootm ''${loadaddr}' 72 ---- 73 74 === Troubleshooting 75 76 The instructions above assume you can boot and SSH into the (recovery) 77 OpenWrt installation. If you have broken your device to the point where 78 that is no longer possible, you could re-install OpenWrt, but probably 79 you could also install directly from U-Boot: 80 81 https://github.com/u-boot/u-boot/blob/master/doc/README.ubi 82 ''; 83 84 system = { 85 crossSystem = { 86 config = "aarch64-unknown-linux-musl"; 87 gcc = { 88 # https://openwrt.org/docs/techref/instructionset/aarch64_cortex-a53 89 # openwrt ./target/linux/mediatek/filogic/target.mk 90 # https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html 91 # https://en.wikipedia.org/wiki/Comparison_of_ARM_processors 92 arch = "armv8-a"; 93 }; 94 }; 95 }; 96 97 module = 98 { 99 pkgs, 100 config, 101 lib, 102 lim, 103 ... 104 }: 105 let 106 openwrt = pkgs.openwrt_25_12; 107 mediatek-firmware = pkgs.stdenv.mkDerivation { 108 name = "wlan-firmware"; 109 phases = [ "installPhase" ]; 110 installPhase = '' 111 mkdir $out 112 113 cp ${pkgs.linux-firmware}/lib/firmware/mediatek/{mt7915,mt7615,mt7986_eeprom_mt7976,mt7981}* $out 114 ''; 115 }; 116 airoha-firmware = pkgs.stdenv.mkDerivation { 117 name = "airoha-firmware"; 118 phases = [ "installPhase" ]; 119 installPhase = '' 120 mkdir $out 121 122 cp -r ${pkgs.linux-firmware}/lib/firmware/airoha/* $out 123 ''; 124 }; 125 in 126 { 127 imports = [ 128 ../../modules/arch/aarch64.nix 129 ../../modules/outputs/tftpboot.nix 130 ../../modules/outputs/ubifs.nix 131 ]; 132 config = { 133 kernel = { 134 src = openwrt.kernelSrc; 135 version = openwrt.kernelVersion; 136 extraPatchPhase = '' 137 ${openwrt.applyPatches.mediatek} 138 ''; 139 config = { 140 NET = "y"; # unlock NET_XGRESS 141 SERIAL_8250 = "y"; # unlock SERIAL_8250_FSL 142 SERIAL_8250_CONSOLE = "y"; # to get the serial console 143 WATCHDOG = "y"; # unlock WATCHDOG_CORE 144 NEW_LEDS = "y"; # unlock LEDS_PWM 145 LEDS_CLASS = "y"; # unlock LEDS_PWM 146 LEDS_TRIGGERS = "y"; # unlock LEDS_TRIGGER_PATTERN 147 DEFERRED_STRUCT_PAGE_INIT = "y"; # trigger PADATA 148 # Taken from openwrt's ./target/linux/mediatek/filogic/config-6.6 149 "64BIT" = "y"; 150 AIROHA_EN8801SC_PHY = "y"; 151 ARCH_BINFMT_ELF_EXTRA_PHDRS = "y"; 152 ARCH_CORRECT_STACKTRACE_ON_KRETPROBE = "y"; 153 ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG = "y"; 154 ARCH_DMA_ADDR_T_64BIT = "y"; 155 ARCH_KEEP_MEMBLOCK = "y"; 156 ARCH_MEDIATEK = "y"; 157 ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE = "y"; 158 ARCH_PROC_KCORE_TEXT = "y"; 159 ARCH_SPARSEMEM_ENABLE = "y"; 160 ARCH_STACKWALK = "y"; 161 ARCH_SUSPEND_POSSIBLE = "y"; 162 ARCH_WANTS_NO_INSTR = "y"; 163 ARM64 = "y"; 164 ARM64_ERRATUM_843419 = "y"; 165 ARM64_LD_HAS_FIX_ERRATUM_843419 = "y"; 166 ARM64_TAGGED_ADDR_ABI = "y"; 167 ARM_AMBA = "y"; 168 ARM_ARCH_TIMER = "y"; 169 ARM_ARCH_TIMER_EVTSTREAM = "y"; 170 ARM_GIC = "y"; 171 ARM_GIC_V2M = "y"; 172 ARM_GIC_V3 = "y"; 173 ARM_GIC_V3_ITS = "y"; 174 ARM_MEDIATEK_CCI_DEVFREQ = "y"; 175 ARM_MEDIATEK_CPUFREQ = "y"; 176 ARM_PMU = "y"; 177 ARM_PMUV3 = "y"; 178 ARM_PSCI_FW = "y"; 179 ATA = "y"; 180 AUDIT_ARCH_COMPAT_GENERIC = "y"; 181 BLK_DEV_LOOP = "y"; 182 BLK_DEV_SD = "y"; 183 BLK_MQ_PCI = "y"; 184 BLK_PM = "y"; 185 BLOCK_NOTIFIERS = "y"; 186 BSD_PROCESS_ACCT = "y"; 187 BSD_PROCESS_ACCT_V3 = "y"; 188 BUFFER_HEAD = "y"; 189 BUILTIN_RETURN_ADDRESS_STRIPS_PAC = "y"; 190 CC_HAVE_SHADOW_CALL_STACK = "y"; 191 CC_HAVE_STACKPROTECTOR_SYSREG = "y"; 192 #CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"; 193 CLKSRC_MMIO = "y"; 194 CLONE_BACKWARDS = "y"; 195 CMDLINE_OVERRIDE = "y"; 196 COMMON_CLK = "y"; 197 COMMON_CLK_MEDIATEK = "y"; 198 COMMON_CLK_MT7981 = "y"; 199 COMMON_CLK_MT7981_ETHSYS = "y"; 200 COMMON_CLK_MT7986 = "y"; 201 COMMON_CLK_MT7986_ETHSYS = "y"; 202 COMMON_CLK_MT7988 = "y"; 203 COMPACT_UNEVICTABLE_DEFAULT = "1"; 204 CONFIGFS_FS = "y"; 205 CONSOLE_LOGLEVEL_DEFAULT = "15"; 206 CONTEXT_TRACKING = "y"; 207 CONTEXT_TRACKING_IDLE = "y"; 208 CPU_FREQ = "y"; 209 CPU_FREQ_DEFAULT_GOV_USERSPACE = "y"; 210 CPU_FREQ_GOV_ATTR_SET = "y"; 211 CPU_FREQ_GOV_COMMON = "y"; 212 CPU_FREQ_GOV_CONSERVATIVE = "y"; 213 CPU_FREQ_GOV_ONDEMAND = "y"; 214 CPU_FREQ_GOV_PERFORMANCE = "y"; 215 CPU_FREQ_GOV_POWERSAVE = "y"; 216 CPU_FREQ_GOV_SCHEDUTIL = "y"; 217 CPU_FREQ_GOV_USERSPACE = "y"; 218 CPU_FREQ_STAT = "y"; 219 CPU_LITTLE_ENDIAN = "y"; 220 CPU_RMAP = "y"; 221 CPU_THERMAL = "y"; 222 CRC16 = "y"; 223 CRC_CCITT = "y"; 224 CRYPTO_AES_ARM64 = "y"; 225 CRYPTO_AES_ARM64_CE = "y"; 226 CRYPTO_AES_ARM64_CE_BLK = "y"; 227 CRYPTO_AES_ARM64_CE_CCM = "y"; 228 CRYPTO_CMAC = "y"; 229 CRYPTO_CRC32 = "y"; 230 CRYPTO_CRC32C = "y"; 231 CRYPTO_CRYPTD = "y"; 232 CRYPTO_DEFLATE = "y"; 233 CRYPTO_DRBG = "y"; 234 CRYPTO_DRBG_HMAC = "y"; 235 CRYPTO_DRBG_MENU = "y"; 236 CRYPTO_ECB = "y"; 237 CRYPTO_ECC = "y"; 238 CRYPTO_ECDH = "y"; 239 CRYPTO_GHASH_ARM64_CE = "y"; 240 CRYPTO_HASH_INFO = "y"; 241 CRYPTO_HMAC = "y"; 242 CRYPTO_JITTERENTROPY = "y"; 243 CRYPTO_LIB_BLAKE2S_GENERIC = "y"; 244 CRYPTO_LIB_GF128MUL = "y"; 245 CRYPTO_LIB_SHA1 = "y"; 246 CRYPTO_LIB_SHA256 = "y"; 247 CRYPTO_LIB_UTILS = "y"; 248 CRYPTO_LZO = "y"; 249 CRYPTO_RNG = "y"; 250 CRYPTO_RNG2 = "y"; 251 CRYPTO_RNG_DEFAULT = "y"; 252 CRYPTO_SHA256 = "y"; 253 CRYPTO_SHA256_ARM64 = "y"; 254 CRYPTO_SHA2_ARM64_CE = "y"; 255 CRYPTO_SHA3 = "y"; 256 CRYPTO_SHA512 = "y"; 257 CRYPTO_SM4 = "y"; 258 CRYPTO_SM4_ARM64_CE_BLK = "y"; 259 CRYPTO_SM4_ARM64_CE_CCM = "y"; 260 CRYPTO_SM4_ARM64_CE_GCM = "y"; 261 CRYPTO_ZSTD = "y"; 262 DCACHE_WORD_ACCESS = "y"; 263 #DEBUG_INFO="y"; 264 DEBUG_MISC = "y"; 265 DEVFREQ_GOV_PASSIVE = "y"; 266 DIMLIB = "y"; 267 DMADEVICES = "y"; 268 DMATEST = "y"; 269 DMA_BOUNCE_UNALIGNED_KMALLOC = "y"; 270 DMA_DIRECT_REMAP = "y"; 271 DMA_ENGINE = "y"; 272 DMA_ENGINE_RAID = "y"; 273 DMA_OF = "y"; 274 DMA_VIRTUAL_CHANNELS = "y"; 275 DTC = "y"; 276 EDAC_SUPPORT = "y"; 277 EINT_MTK = "y"; 278 EXCLUSIVE_SYSTEM_RAM = "y"; 279 EXT4_FS = "y"; 280 F2FS_FS = "y"; 281 FIXED_PHY = "y"; 282 FIX_EARLYCON_MEM = "y"; 283 FRAME_POINTER = "y"; 284 FS_IOMAP = "y"; 285 FS_MBCACHE = "y"; 286 FUNCTION_ALIGNMENT = "4"; 287 FUNCTION_ALIGNMENT_4B = "y"; 288 FWNODE_MDIO = "y"; 289 FW_LOADER_PAGED_BUF = "y"; 290 #FW_LOADER_SYSFS="y"; 291 #GCC11_NO_ARRAY_BOUNDS="y"; 292 #GCC_ASM_GOTO_OUTPUT_WORKAROUND="y"; 293 GENERIC_ALLOCATOR = "y"; 294 GENERIC_ARCH_TOPOLOGY = "y"; 295 GENERIC_BUG = "y"; 296 GENERIC_BUG_RELATIVE_POINTERS = "y"; 297 GENERIC_CLOCKEVENTS = "y"; 298 GENERIC_CLOCKEVENTS_BROADCAST = "y"; 299 GENERIC_CPU_AUTOPROBE = "y"; 300 GENERIC_CPU_VULNERABILITIES = "y"; 301 GENERIC_CSUM = "y"; 302 GENERIC_EARLY_IOREMAP = "y"; 303 GENERIC_GETTIMEOFDAY = "y"; 304 GENERIC_IDLE_POLL_SETUP = "y"; 305 GENERIC_IOREMAP = "y"; 306 GENERIC_IRQ_EFFECTIVE_AFF_MASK = "y"; 307 GENERIC_IRQ_SHOW = "y"; 308 GENERIC_IRQ_SHOW_LEVEL = "y"; 309 GENERIC_LIB_DEVMEM_IS_ALLOWED = "y"; 310 GENERIC_MSI_IRQ = "y"; 311 GENERIC_PCI_IOMAP = "y"; 312 GENERIC_PHY = "y"; 313 GENERIC_PINCONF = "y"; 314 GENERIC_PINCTRL_GROUPS = "y"; 315 GENERIC_PINMUX_FUNCTIONS = "y"; 316 GENERIC_SCHED_CLOCK = "y"; 317 GENERIC_SMP_IDLE_THREAD = "y"; 318 GENERIC_STRNCPY_FROM_USER = "y"; 319 GENERIC_STRNLEN_USER = "y"; 320 GENERIC_TIME_VSYSCALL = "y"; 321 GLOB = "y"; 322 GPIO_CDEV = "y"; 323 GPIO_WATCHDOG = "y"; 324 GPIO_WATCHDOG_ARCH_INITCALL = "y"; 325 GRO_CELLS = "y"; 326 HARDIRQS_SW_RESEND = "y"; 327 HAS_DMA = "y"; 328 HAS_IOMEM = "y"; 329 HAS_IOPORT = "y"; 330 HAS_IOPORT_MAP = "y"; 331 HWMON = "y"; 332 HW_RANDOM = "y"; 333 HW_RANDOM_MTK = "y"; 334 I2C = "y"; 335 I2C_BOARDINFO = "y"; 336 I2C_CHARDEV = "y"; 337 I2C_MT65XX = "y"; 338 ICPLUS_PHY = "y"; 339 ILLEGAL_POINTER_VALUE = "0xdead000000000000"; 340 #INITRAMFS_SOURCE=""""; 341 IRQCHIP = "y"; 342 IRQ_DOMAIN = "y"; 343 IRQ_DOMAIN_HIERARCHY = "y"; 344 IRQ_FORCED_THREADING = "y"; 345 IRQ_TIME_ACCOUNTING = "y"; 346 IRQ_WORK = "y"; 347 JBD2 = "y"; 348 JUMP_LABEL = "y"; 349 LEDS_PWM = "y"; 350 LEDS_SMARTRG_LED = "y"; 351 LEDS_TRIGGER_PATTERN = "y"; 352 LIBFDT = "y"; 353 LOCK_DEBUGGING_SUPPORT = "y"; 354 LOCK_SPIN_ON_OWNER = "y"; 355 LZO_COMPRESS = "y"; 356 LZO_DECOMPRESS = "y"; 357 MAGIC_SYSRQ = "y"; 358 MAXLINEAR_GPHY = "y"; 359 MDIO_BUS = "y"; 360 MDIO_DEVICE = "y"; 361 MDIO_DEVRES = "y"; 362 MEDIATEK_2P5GE_PHY = "y"; 363 MEDIATEK_GE_PHY = "y"; 364 MEDIATEK_GE_SOC_PHY = "y"; 365 MEDIATEK_WATCHDOG = "y"; 366 MESSAGE_LOGLEVEL_DEFAULT = "7"; 367 MFD_SYSCON = "y"; 368 MIGRATION = "y"; 369 MMC = "y"; 370 MMC_BLOCK = "y"; 371 MMC_CQHCI = "y"; 372 MMC_MTK = "y"; 373 MMU_LAZY_TLB_REFCOUNT = "y"; 374 MODULES_TREE_LOOKUP = "y"; 375 MODULES_USE_ELF_RELA = "y"; 376 MTD_NAND_CORE = "y"; 377 MTD_NAND_ECC = "y"; 378 MTD_NAND_ECC_MEDIATEK = "y"; 379 MTD_NAND_ECC_SW_HAMMING = "y"; 380 MTD_NAND_MTK = "y"; 381 MTD_NAND_MTK_BMT = "y"; 382 MTD_PARSER_TRX = "y"; 383 MTD_RAW_NAND = "y"; 384 MTD_SPI_NAND = "y"; 385 MTD_SPI_NOR = "y"; 386 MTD_SPLIT_FIRMWARE = "y"; 387 MTD_SPLIT_FIT_FW = "y"; 388 MTD_SPLIT_MSTC_BOOT = "y"; 389 MTD_UBI = "y"; 390 MTD_UBI_BEB_LIMIT = "20"; 391 MTD_UBI_BLOCK = "y"; 392 MTD_UBI_FASTMAP = "y"; 393 MTD_UBI_NVMEM = "y"; 394 MTD_UBI_WL_THRESHOLD = "4096"; 395 MTK_CPUX_TIMER = "y"; 396 MTK_HSDMA = "y"; 397 MTK_INFRACFG = "y"; 398 MTK_LVTS_THERMAL = "y"; 399 MTK_LVTS_THERMAL_DEBUGFS = "y"; 400 MTK_PMIC_WRAP = "y"; 401 MTK_REGULATOR_COUPLER = "y"; 402 MTK_SCPSYS = "y"; 403 MTK_SCPSYS_PM_DOMAINS = "y"; 404 MTK_SOC_THERMAL = "y"; 405 MTK_THERMAL = "y"; 406 MTK_TIMER = "y"; 407 MUTEX_SPIN_ON_OWNER = "y"; 408 NEED_DMA_MAP_STATE = "y"; 409 NEED_SG_DMA_LENGTH = "y"; 410 NET_DEVLINK = "y"; 411 NET_DSA = "y"; 412 NET_DSA_MT7530 = "y"; 413 NET_DSA_MT7530_MDIO = "y"; 414 NET_DSA_MT7530_MMIO = "y"; 415 NET_DSA_TAG_MTK = "y"; 416 #NET_EGRESS="y"; 417 NET_FLOW_LIMIT = "y"; 418 #NET_INGRESS="y"; 419 NET_MEDIATEK_SOC = "y"; 420 NET_MEDIATEK_SOC_WED = "y"; 421 NET_SELFTESTS = "y"; 422 NET_SWITCHDEV = "y"; 423 NET_VENDOR_MEDIATEK = "y"; 424 #NET_XGRESS="y"; 425 NLS = "y"; 426 NO_HZ_COMMON = "y"; 427 NO_HZ_IDLE = "y"; 428 NR_CPUS = "4"; 429 NVMEM = "y"; 430 NVMEM_BLOCK = "y"; 431 NVMEM_LAYOUTS = "y"; 432 NVMEM_LAYOUT_ADTRAN = "y"; 433 NVMEM_MTK_EFUSE = "y"; 434 NVMEM_SYSFS = "y"; 435 OF = "y"; 436 OF_ADDRESS = "y"; 437 OF_DYNAMIC = "y"; 438 OF_EARLY_FLATTREE = "y"; 439 OF_FLATTREE = "y"; 440 OF_GPIO = "y"; 441 OF_IRQ = "y"; 442 OF_KOBJ = "y"; 443 OF_MDIO = "y"; 444 OF_OVERLAY = "y"; 445 OF_RESOLVE = "y"; 446 PADATA = "y"; 447 PAGE_POOL = "y"; 448 PAGE_POOL_STATS = "y"; 449 #PAHOLE_HAS_LANG_EXCLUDE="y"; 450 PARTITION_PERCPU = "y"; 451 PCI = "y"; 452 PCIEAER = "y"; 453 PCIEASPM = "y"; 454 PCIEASPM_PERFORMANCE = "y"; 455 PCIEPORTBUS = "y"; 456 PCIE_MEDIATEK_GEN3 = "y"; 457 PCIE_PME = "y"; 458 PCI_DEBUG = "y"; 459 PCI_DOMAINS = "y"; 460 PCI_DOMAINS_GENERIC = "y"; 461 PCI_MSI = "y"; 462 PCS_MTK_LYNXI = "y"; 463 PCS_MTK_USXGMII = "y"; 464 PERF_EVENTS = "y"; 465 PER_VMA_LOCK = "y"; 466 PHYLIB = "y"; 467 PHYLIB_LEDS = "y"; 468 PHYLINK = "y"; 469 PHYS_ADDR_T_64BIT = "y"; 470 PHY_MTK_TPHY = "y"; 471 PHY_MTK_XFI_TPHY = "y"; 472 PHY_MTK_XSPHY = "y"; 473 PINCTRL = "y"; 474 PINCTRL_MT7981 = "y"; 475 PINCTRL_MT7986 = "y"; 476 PINCTRL_MT7988 = "y"; 477 PINCTRL_MTK_MOORE = "y"; 478 PINCTRL_MTK_V2 = "y"; 479 PM = "y"; 480 PM_CLK = "y"; 481 PM_DEVFREQ = "y"; 482 PM_DEVFREQ_EVENT = "y"; 483 PM_GENERIC_DOMAINS = "y"; 484 PM_GENERIC_DOMAINS_OF = "y"; 485 PM_OPP = "y"; 486 POLYNOMIAL = "y"; 487 POSIX_CPU_TIMERS_TASK_WORK = "y"; 488 POWER_RESET = "y"; 489 POWER_RESET_SYSCON = "y"; 490 POWER_SUPPLY = "y"; 491 PREEMPT_NONE_BUILD = "y"; 492 PRINTK_TIME = "y"; 493 PSTORE = "y"; 494 PSTORE_COMPRESS = "y"; 495 PSTORE_CONSOLE = "y"; 496 PSTORE_PMSG = "y"; 497 PSTORE_RAM = "y"; 498 PTP_1588_CLOCK_OPTIONAL = "y"; 499 PWM = "y"; 500 PWM_MEDIATEK = "y"; 501 QUEUED_RWLOCKS = "y"; 502 QUEUED_SPINLOCKS = "y"; 503 RANDSTRUCT_NONE = "y"; 504 RAS = "y"; 505 RATIONAL = "y"; 506 REALTEK_PHY = "y"; 507 REED_SOLOMON = "y"; 508 REED_SOLOMON_DEC8 = "y"; 509 REED_SOLOMON_ENC8 = "y"; 510 REGMAP = "y"; 511 REGMAP_I2C = "y"; 512 REGMAP_MMIO = "y"; 513 REGULATOR = "y"; 514 REGULATOR_FIXED_VOLTAGE = "y"; 515 REGULATOR_MT6380 = "y"; 516 REGULATOR_RT5190A = "y"; 517 RESET_CONTROLLER = "y"; 518 RESET_TI_SYSCON = "y"; 519 RFS_ACCEL = "y"; 520 RODATA_FULL_DEFAULT_ENABLED = "y"; 521 RPS = "y"; 522 RTC_CLASS = "y"; 523 RTC_DRV_MT7622 = "y"; 524 RTC_I2C_AND_SPI = "y"; 525 RWSEM_SPIN_ON_OWNER = "y"; 526 SCHED_MC = "y"; 527 SCSI = "y"; 528 SCSI_COMMON = "y"; 529 SERIAL_8250_FSL = "y"; 530 SERIAL_8250_MT6577 = "y"; 531 SERIAL_8250_NR_UARTS = "3"; 532 SERIAL_8250_RUNTIME_UARTS = "3"; 533 SERIAL_DEV_BUS = "y"; 534 SERIAL_DEV_CTRL_TTYPORT = "y"; 535 SERIAL_MCTRL_GPIO = "y"; 536 SERIAL_OF_PLATFORM = "y"; 537 SGL_ALLOC = "y"; 538 SG_POOL = "y"; 539 SMP = "y"; 540 SOCK_RX_QUEUE_MAPPING = "y"; 541 SOFTIRQ_ON_OWN_STACK = "y"; 542 SPARSEMEM = "y"; 543 SPARSEMEM_EXTREME = "y"; 544 SPARSEMEM_VMEMMAP = "y"; 545 SPARSEMEM_VMEMMAP_ENABLE = "y"; 546 SPARSE_IRQ = "y"; 547 SPI = "y"; 548 SPI_DYNAMIC = "y"; 549 SPI_MASTER = "y"; 550 SPI_MEM = "y"; 551 SPI_MT65XX = "y"; 552 SPI_MTK_SNFI = "y"; 553 #SQUASHFS_DECOMP_MULTI_PERCPU="y"; 554 SWIOTLB = "y"; 555 SWPHY = "y"; 556 SYSCTL_EXCEPTION_TRACE = "y"; 557 THERMAL = "y"; 558 THERMAL_DEFAULT_GOV_STEP_WISE = "y"; 559 THERMAL_EMERGENCY_POWEROFF_DELAY_MS = "0"; 560 THERMAL_GOV_BANG_BANG = "y"; 561 THERMAL_GOV_FAIR_SHARE = "y"; 562 THERMAL_GOV_STEP_WISE = "y"; 563 THERMAL_GOV_USER_SPACE = "y"; 564 THERMAL_HWMON = "y"; 565 THERMAL_OF = "y"; 566 THREAD_INFO_IN_TASK = "y"; 567 TICK_CPU_ACCOUNTING = "y"; 568 TIMER_OF = "y"; 569 TIMER_PROBE = "y"; 570 TRACE_IRQFLAGS_NMI_SUPPORT = "y"; 571 TREE_RCU = "y"; 572 TREE_SRCU = "y"; 573 UBIFS_FS = "y"; 574 UIMAGE_FIT_BLK = "y"; 575 USB_SUPPORT = "y"; 576 VMAP_STACK = "y"; 577 WATCHDOG_CORE = "y"; 578 WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC = "y"; 579 WATCHDOG_PRETIMEOUT_GOV = "y"; 580 WATCHDOG_PRETIMEOUT_GOV_PANIC = "y"; 581 WATCHDOG_PRETIMEOUT_GOV_SEL = "m"; 582 WATCHDOG_SYSFS = "y"; 583 XPS = "y"; 584 XXHASH = "y"; 585 ZLIB_DEFLATE = "y"; 586 ZLIB_INFLATE = "y"; 587 ZONE_DMA32 = "y"; 588 ZSTD_COMMON = "y"; 589 ZSTD_COMPRESS = "y"; 590 ZSTD_DECOMPRESS = "y"; 591 # from DEVICE_PACKAGES in the openwrt_one section of 592 # openwrt's ./target/linux/mediatek/image/filogic.mk: 593 # chop off the 'kmod-' prefix and search for 'KernelPackage/...' 594 # in ./package/kernel/linux/modules/*.mk, and remember to add 595 # modules to kmodloader targets below 596 AIR_EN8811H_PHY = "m"; 597 RTC_DRV_PCF8563 = "m"; 598 NVME_CORE = "m"; 599 BLK_DEV_NVME = "m"; 600 NVME_MULTIPATH = "n"; 601 NVME_HWMON = "y"; 602 # ??? 603 AQUANTIA_PHY = "m"; 604 MT798X_WMAC = "y"; 605 } 606 // lib.optionalAttrs (config.system.service ? watchdog) { 607 RALINK_WDT = "y"; # watchdog 608 MT7621_WDT = "y"; # or it might be this one 609 }; 610 conditionalConfig = { 611 WLAN = { 612 MT7915E = "m"; 613 }; 614 }; 615 }; 616 boot = { 617 commandLine = [ "console=ttyS0,115200" ]; 618 tftp = { 619 # Should be a segment of free RAM, where the tftp artifact 620 # can be stored before unpacking it to the 'hardware.loadAddress' 621 # This address is after the reserved-memory regions in both 622 # the kernel and OpenWrt's fork of U-Boot. 623 # https://github.com/torvalds/linux/blob/897d54018cc9aa97fd1529ca08a53b429d05a566/arch/arm64/boot/dts/mediatek/mt7981b.dtsi#L72 624 # https://github.com/openwrt/openwrt/blob/14a27ac99d627db519ab3454d98155567c4a8d88/package/boot/uboot-mediatek/patches/052-mt7981-enable-pstore.patch#L30 625 loadAddress = lim.parseInt "0x50000000"; 626 }; 627 imageFormat = "fit"; 628 loader.fit.enable = lib.mkDefault true; # override this if you are building tftpboot 629 }; 630 rootfsType = lib.mkDefault "ubifs"; # override this if you are building tftpboot 631 filesystem = 632 let 633 inherit (pkgs.pseudofile) dir symlink; 634 in 635 dir { 636 lib = dir { 637 firmware = dir { 638 mediatek = symlink mediatek-firmware; 639 airoha = symlink airoha-firmware; 640 }; 641 }; 642 }; 643 644 hardware = 645 let 646 phy = pkgs.kmodloader.override { 647 targets = [ 648 "air_en8811h" 649 ]; 650 inherit (config.system.outputs) kernel; 651 }; 652 mac80211 = pkgs.kmodloader.override { 653 targets = [ 654 "mt7915e" 655 "rtc-pcf8563" 656 "nvme_core" 657 "nvme" 658 #"mt7996e" 659 "aquantia" 660 ]; 661 inherit (config.system.outputs) kernel; 662 }; 663 in 664 { 665 # from OEM bootlog 666 # Creating 4 MTD partitions on "spi0.0": 667 # 0x000000000000-0x000000040000 : "bl2-nor" 668 # 0x000000040000-0x000000100000 : "factory" 669 # 0x000000100000-0x000000180000 : "fip-nor" 670 # 0x000000180000-0x000000e00000 : "recovery" 671 # spi-nand spi1.1: calibration result: 0x3 672 # spi-nand spi1.1: Winbond SPI NAND was found. 673 # spi-nand spi1.1: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128 674 # 2 fixed-partitions partitions found on MTD device spi1.1 675 # Creating 2 MTD partitions on "spi1.1": 676 # 0x000000000000-0x000000100000 : "bl2" 677 # 0x000000100000-0x000010000000 : "ubi" 678 679 flash = { 680 # from the OEM bootlog: 681 # ## Checking Image at 46000000 ... 682 # FIT image found 683 # FIT description: ARM64 OpenWrt FIT (Flattened Image Tree) 684 # Image 0 (kernel-1) 685 # Description: ARM64 OpenWrt Linux-6.6.57 686 # Type: Kernel Image 687 # Compression: gzip compressed 688 # Data Start: 0x46001000 689 # Data Size: 5751840 Bytes = 5.5 MiB 690 # Architecture: AArch64 691 # OS: Linux 692 # Load Address: 0x44000000 693 # Entry Point: 0x44000000 694 695 address = lim.parseInt "0x44000000"; 696 size = lim.parseInt "0xf60000"; 697 # /proc/mtd on a running system: 698 # dev: size erasesize name 699 # mtd0: 00040000 00010000 "bl2-nor" 700 # mtd1: 000c0000 00010000 "factory" 701 # mtd2: 00080000 00010000 "fip-nor" 702 # mtd3: 00c80000 00010000 "recovery" 703 # mtd4: 00100000 00020000 "bl2" 704 # mtd5: 0ff00000 00020000 "ubi" 705 eraseBlockSize = 65536; 706 }; 707 ubi = { 708 # TODO taken from belkin-rt3200, to review 709 minIOSize = "2048"; 710 logicalEraseBlockSize = "126976"; 711 physicalEraseBlockSize = "131072"; 712 maxLEBcount = "1400"; # guessing 713 }; 714 715 defaultOutput = "ubimage"; 716 loadAddress = lim.parseInt "0x44000000"; 717 entryPoint = lim.parseInt "0x44000000"; 718 # TODO AFAICT this should be 2048, but I got 'FIT: image rootfs-1 start not aligned to page boundaries' with that... 719 #alignment = 2048; 720 alignment = 4096; 721 rootDevice = "ubi0:liminix"; 722 dts = { 723 src = "${openwrt.src}/target/linux/mediatek/dts/mt7981b-openwrt-one.dts"; 724 includePaths = [ 725 "${openwrt.src}/target/linux/mediatek/dts" 726 "${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/" 727 ]; 728 }; 729 730 networkInterfaces = 731 let 732 inherit (config.system.service.network) link; 733 in 734 rec { 735 eth0 = link.build { 736 ifname = "eth0"; 737 dependencies = [ phy ]; 738 }; 739 eth1 = link.build { ifname = "eth1"; }; 740 741 wlan0 = link.build { 742 ifname = "wlan0"; 743 dependencies = [ mac80211 ]; 744 }; 745 wlan1 = link.build { 746 ifname = "wlan1"; 747 dependencies = [ mac80211 ]; 748 }; 749 }; 750 }; 751 }; 752 }; 753 }