default.nix (15218B)
1 { 2 description = '' 3 TP-Link Archer AX23 / AX1800 Dual Band Wi-Fi 6 Router 4 ***************************************************** 5 6 Hardware summary 7 ================ 8 9 - MediaTek MT7621 (880MHz) 10 - 16MB Flash 11 - 128MB RAM 12 - WLan hardware: Mediatek MT7905, MT7975 13 14 Limitations 15 =========== 16 17 Status LEDs do not work yet. 18 19 Uploading an image via tftp doesn't work yet, because the Archer uboot 20 version is so old it doesn't support overriding the DTB from the mboot 21 command. The tftpboot module doesn't support this yet, see 22 https://gti.telent.net/dan/liminix/pulls/5 for the WiP. 23 ''; 24 25 system = { 26 crossSystem = { 27 config = "mipsel-unknown-linux-musl"; 28 gcc = { 29 abi = "32"; 30 # https://openwrt.org/docs/techref/instructionset/mipsel_24kc 31 arch = "24kc"; 32 }; 33 }; 34 }; 35 36 module = {pkgs, config, lib, lim, ... }: 37 let firmware = pkgs.stdenv.mkDerivation { 38 name = "wlan-firmware"; 39 phases = ["installPhase"]; 40 installPhase = '' 41 mkdir $out 42 cp ${pkgs.linux-firmware}/lib/firmware/mediatek/{mt7915,mt7615,mt7622}* $out 43 ''; 44 }; 45 in { 46 imports = [ 47 ../../modules/arch/mipsel.nix 48 ../../modules/outputs/tftpboot.nix 49 ../../modules/outputs/tplink-safeloader.nix 50 ]; 51 config = { 52 kernel = { 53 src = pkgs.pkgsBuildBuild.fetchurl { 54 name = "linux.tar.gz"; 55 url = "https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.15.137.tar.gz"; 56 hash = "sha256-PkdzUKZ0IpBiWe/RS70J76JKnBFzRblWcKlaIFNxnHQ="; 57 }; 58 extraPatchPhase = '' 59 ${pkgs.openwrt.applyPatches.ramips} 60 ''; 61 config = { 62 # Initially taken from openwrt's ./target/linux/ramips/mt7621/config-5.15, 63 # then tweaked here and there 64 ARCH_32BIT_OFF_T="y"; 65 ARCH_HIBERNATION_POSSIBLE="y"; 66 ARCH_KEEP_MEMBLOCK="y"; 67 ARCH_MMAP_RND_BITS_MAX="15"; 68 ARCH_MMAP_RND_COMPAT_BITS_MAX="15"; 69 ARCH_SUSPEND_POSSIBLE="y"; 70 AT803X_PHY="y"; 71 BLK_MQ_PCI="y"; 72 BOARD_SCACHE="y"; 73 CEVT_R4K="y"; 74 CLKSRC_MIPS_GIC="y"; 75 CLK_MT7621="y"; 76 CLOCKSOURCE_WATCHDOG="y"; 77 CLONE_BACKWARDS="y"; 78 CMDLINE_BOOL="y"; 79 COMMON_CLK="y"; 80 COMPAT_32BIT_TIME="y"; 81 CPU_GENERIC_DUMP_TLB="y"; 82 CPU_HAS_DIEI="y"; 83 CPU_HAS_PREFETCH="y"; 84 CPU_HAS_RIXI="y"; 85 CPU_HAS_SYNC="y"; 86 CPU_LITTLE_ENDIAN="y"; 87 CPU_MIPS32="y"; 88 CPU_MIPS32_R2="y"; 89 CPU_MIPSR2="y"; 90 CPU_MIPSR2_IRQ_EI="y"; 91 CPU_MIPSR2_IRQ_VI="y"; 92 CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS="y"; 93 CPU_R4K_CACHE_TLB="y"; 94 CPU_RMAP="y"; 95 CPU_SUPPORTS_32BIT_KERNEL="y"; 96 CPU_SUPPORTS_HIGHMEM="y"; 97 CPU_SUPPORTS_MSA="y"; 98 CRC16="y"; 99 CRYPTO_DEFLATE="y"; 100 CRYPTO_HASH_INFO="y"; 101 CRYPTO_LIB_BLAKE2S_GENERIC="y"; 102 CRYPTO_LIB_POLY1305_RSIZE="2"; 103 CRYPTO_LZO="y"; 104 CRYPTO_ZSTD="y"; 105 CSRC_R4K="y"; 106 DIMLIB="y"; 107 DMA_NONCOHERENT="y"; 108 DTB_RT_NONE="y"; 109 DTC="y"; 110 EARLY_PRINTK="y"; 111 FIXED_PHY="y"; 112 FWNODE_MDIO="y"; 113 FW_LOADER_PAGED_BUF="y"; 114 GENERIC_ATOMIC64="y"; 115 GENERIC_CLOCKEVENTS="y"; 116 GENERIC_CMOS_UPDATE="y"; 117 GENERIC_CPU_AUTOPROBE="y"; 118 GENERIC_FIND_FIRST_BIT="y"; 119 GENERIC_GETTIMEOFDAY="y"; 120 GENERIC_IOMAP="y"; 121 GENERIC_IRQ_CHIP="y"; 122 GENERIC_IRQ_EFFECTIVE_AFF_MASK="y"; 123 GENERIC_IRQ_SHOW="y"; 124 GENERIC_LIB_ASHLDI3="y"; 125 GENERIC_LIB_ASHRDI3="y"; 126 GENERIC_LIB_CMPDI2="y"; 127 GENERIC_LIB_LSHRDI3="y"; 128 GENERIC_LIB_UCMPDI2="y"; 129 GENERIC_PCI_IOMAP="y"; 130 GENERIC_PHY="y"; 131 GENERIC_PINCONF="y"; 132 GENERIC_SCHED_CLOCK="y"; 133 GENERIC_SMP_IDLE_THREAD="y"; 134 GENERIC_TIME_VSYSCALL="y"; 135 GLOB="y"; 136 GPIOLIB_IRQCHIP="y"; 137 GPIO_CDEV="y"; 138 GPIO_GENERIC="y"; 139 GPIO_MT7621="y"; 140 GRO_CELLS="y"; 141 HANDLE_DOMAIN_IRQ="y"; 142 HARDWARE_WATCHPOINTS="y"; 143 HAS_DMA="y"; 144 HAS_IOMEM="y"; 145 HAS_IOPORT_MAP="y"; 146 I2C="y"; 147 I2C_ALGOBIT="y"; 148 I2C_BOARDINFO="y"; 149 I2C_CHARDEV="y"; 150 I2C_GPIO="y"; 151 I2C_MT7621="y"; 152 ICPLUS_PHY="y"; 153 IRQCHIP="y"; 154 IRQ_DOMAIN="y"; 155 IRQ_DOMAIN_HIERARCHY="y"; 156 IRQ_FORCED_THREADING="y"; 157 IRQ_MIPS_CPU="y"; 158 IRQ_WORK="y"; 159 LIBFDT="y"; 160 LOCK_DEBUGGING_SUPPORT="y"; 161 LZO_COMPRESS="y"; 162 LZO_DECOMPRESS="y"; 163 MDIO_BUS="y"; 164 MDIO_DEVICE="y"; 165 MDIO_DEVRES="y"; 166 MEDIATEK_GE_PHY="y"; 167 MEMFD_CREATE="y"; 168 MFD_SYSCON="y"; 169 MIGRATION="y"; 170 MIKROTIK="y"; 171 MIKROTIK_RB_SYSFS="y"; 172 MIPS="y"; 173 MIPS_ASID_BITS="8"; 174 MIPS_ASID_SHIFT="0"; 175 MIPS_CLOCK_VSYSCALL="y"; 176 MIPS_CM="y"; 177 MIPS_CPC="y"; 178 MIPS_CPS="y"; 179 MIPS_CPU_SCACHE="y"; 180 MIPS_GIC="y"; 181 MIPS_L1_CACHE_SHIFT="5"; 182 MIPS_LD_CAN_LINK_VDSO="y"; 183 MIPS_MT="y"; 184 MIPS_MT_FPAFF="y"; 185 MIPS_MT_SMP="y"; 186 MIPS_NR_CPU_NR_MAP="4"; 187 MIPS_PERF_SHARED_TC_COUNTERS="y"; 188 MIPS_SPRAM="y"; 189 MODULES_USE_ELF_REL="y"; 190 MTD_CMDLINE_PARTS="y"; 191 MTD_NAND_CORE="y"; 192 MTD_NAND_ECC="y"; 193 MTD_NAND_ECC_SW_HAMMING="y"; 194 MTD_NAND_MT7621="y"; 195 MTD_NAND_MTK_BMT="y"; 196 MTD_RAW_NAND="y"; 197 MTD_ROUTERBOOT_PARTS="y"; 198 MTD_SERCOMM_PARTS="y"; 199 MTD_SPI_NOR="y"; 200 MTD_SPLIT_FIT_FW="y"; 201 MTD_SPLIT_MINOR_FW="y"; 202 MTD_SPLIT_SEAMA_FW="y"; 203 MTD_SPLIT_TPLINK_FW="y"; 204 MTD_SPLIT_TRX_FW="y"; 205 MTD_SPLIT_UIMAGE_FW="y"; 206 MTD_UBI="y"; 207 MTD_UBI_BEB_LIMIT="20"; 208 MTD_UBI_BLOCK="y"; 209 MTD_UBI_WL_THRESHOLD="4096"; 210 MTD_VIRT_CONCAT="y"; 211 NEED_DMA_MAP_STATE="y"; 212 NET_DEVLINK="y"; 213 NET_DSA="y"; 214 NET_DSA_MT7530="y"; 215 NET_DSA_MT7530_MDIO="y"; 216 NET_DSA_TAG_MTK="y"; 217 NET_FLOW_LIMIT="y"; 218 NET_MEDIATEK_SOC="y"; 219 NET_SELFTESTS="y"; 220 NET_SWITCHDEV="y"; 221 NET_VENDOR_MEDIATEK="y"; 222 NO_HZ_COMMON="y"; 223 NO_HZ_IDLE="y"; 224 NR_CPUS="4"; 225 NVMEM="y"; 226 OF="y"; 227 OF_ADDRESS="y"; 228 OF_EARLY_FLATTREE="y"; 229 OF_FLATTREE="y"; 230 OF_GPIO="y"; 231 OF_IRQ="y"; 232 OF_KOBJ="y"; 233 OF_MDIO="y"; 234 PAGE_POOL="y"; 235 PAGE_POOL_STATS="y"; 236 PCI="y"; 237 PCIE_MT7621="y"; 238 PCI_DISABLE_COMMON_QUIRKS="y"; 239 PCI_DOMAINS="y"; 240 PCI_DOMAINS_GENERIC="y"; 241 PCI_DRIVERS_GENERIC="y"; 242 PCS_MTK_LYNXI="y"; 243 PERF_USE_VMALLOC="y"; 244 PGTABLE_LEVELS="2"; 245 PHYLIB="y"; 246 PHYLINK="y"; 247 PHY_MT7621_PCI="y"; 248 PINCTRL="y"; 249 PINCTRL_AW9523="y"; 250 PINCTRL_MT7621="y"; 251 PINCTRL_RALINK="y"; 252 PINCTRL_SX150X="y"; 253 POWER_RESET="y"; 254 POWER_RESET_GPIO="y"; 255 POWER_SUPPLY="y"; 256 PTP_1588_CLOCK_OPTIONAL="y"; 257 QUEUED_RWLOCKS="y"; 258 QUEUED_SPINLOCKS="y"; 259 RALINK="y"; 260 RATIONAL="y"; 261 REGMAP="y"; 262 REGMAP_I2C="y"; 263 REGMAP_MMIO="y"; 264 REGULATOR="y"; 265 REGULATOR_FIXED_VOLTAGE="y"; 266 RESET_CONTROLLER="y"; 267 RFS_ACCEL="y"; 268 RPS="y"; 269 RTC_CLASS="y"; 270 RTC_DRV_BQ32K="y"; 271 RTC_DRV_PCF8563="y"; 272 RTC_I2C_AND_SPI="y"; 273 SCHED_SMT="y"; 274 SERIAL_8250="y"; 275 SERIAL_8250_CONSOLE="y"; 276 SERIAL_8250_NR_UARTS="3"; 277 SERIAL_8250_RUNTIME_UARTS="3"; 278 SERIAL_MCTRL_GPIO="y"; 279 SERIAL_OF_PLATFORM="y"; 280 SGL_ALLOC="y"; 281 SMP="y"; 282 SMP_UP="y"; 283 SOCK_RX_QUEUE_MAPPING="y"; 284 SOC_BUS="y"; 285 SOC_MT7621="y"; 286 SPI="y"; 287 SPI_MASTER="y"; 288 SPI_MEM="y"; 289 SPI_MT7621="y"; 290 SRCU="y"; 291 SWPHY="y"; 292 SYNC_R4K="y"; 293 SYSCTL_EXCEPTION_TRACE="y"; 294 SYS_HAS_CPU_MIPS32_R1="y"; 295 SYS_HAS_CPU_MIPS32_R2="y"; 296 SYS_HAS_EARLY_PRINTK="y"; 297 SYS_SUPPORTS_32BIT_KERNEL="y"; 298 SYS_SUPPORTS_ARBIT_HZ="y"; 299 SYS_SUPPORTS_HIGHMEM="y"; 300 SYS_SUPPORTS_HOTPLUG_CPU="y"; 301 SYS_SUPPORTS_LITTLE_ENDIAN="y"; 302 SYS_SUPPORTS_MIPS16="y"; 303 SYS_SUPPORTS_MIPS_CPS="y"; 304 SYS_SUPPORTS_MULTITHREADING="y"; 305 SYS_SUPPORTS_SCHED_SMT="y"; 306 SYS_SUPPORTS_SMP="y"; 307 SYS_SUPPORTS_ZBOOT="y"; 308 TARGET_ISA_REV="2"; 309 TICK_CPU_ACCOUNTING="y"; 310 TIMER_OF="y"; 311 TIMER_PROBE="y"; 312 TREE_RCU="y"; 313 TREE_SRCU="y"; 314 UBIFS_FS="y"; 315 USB_SUPPORT="y"; 316 USE_OF="y"; 317 WEAK_ORDERING="y"; 318 XPS="y"; 319 XXHASH="y"; 320 ZLIB_DEFLATE="y"; 321 ZLIB_INFLATE="y"; 322 ZSTD_COMPRESS="y"; 323 ZSTD_DECOMPRESS="y"; 324 } // lib.optionalAttrs (config.system.service ? watchdog) { 325 RALINK_WDT = "y"; # watchdog 326 MT7621_WDT = "y"; # or it might be this one 327 }; 328 conditionalConfig = { 329 WLAN = { 330 MT7915E = "m"; 331 }; 332 }; 333 }; 334 tplink-safeloader.board = "ARCHER-AX23-V1"; 335 boot = { 336 commandLine = [ "console=ttyS0,115200" ]; 337 tftp = { 338 # Should be a segment of free RAM, where the tftp artifact 339 # can be stored before unpacking it to the 'hardware.loadAddress' 340 # The 'hardware.loadAddress' is 0x80001000, which suggests the 341 # RAM would start at 0x8000000 and (being 128MB) go to 342 # to 0x8800000. Let's put it at the 100MB mark at 343 # 0x8000000+0x0640000=0x86400000 344 loadAddress = lim.parseInt "0x86400000"; 345 }; 346 }; 347 filesystem = 348 let inherit (pkgs.pseudofile) dir symlink; 349 in 350 dir { 351 lib = dir { 352 firmware = dir { 353 mediatek = symlink firmware; 354 }; 355 }; 356 }; 357 358 hardware = 359 let 360 openwrt = pkgs.openwrt; 361 mac80211 = pkgs.kmodloader.override { 362 targets = [ 363 "mt7915e" 364 ]; 365 inherit (config.system.outputs) kernel; 366 }; 367 in { 368 # from OEM bootlog (openwrt wiki): 369 # 4 cmdlinepart partitions found on MTD device raspi 370 # Creating 4 MTD partitions on "raspi": 371 # 0x000000000000-0x000000040000 : "uboot" 372 # 0x000000040000-0x000000440000 : "uImage" 373 # 0x000000440000-0x000000ff0000 : "rootfs" 374 # 0x000000ff0000-0x000001000000 : "ART" 375 # from openwrt bootlog (openwrt wiki): 376 # 5 fixed-partitions partitions found on MTD device spi0.0 377 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 378 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 379 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 380 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 381 # Creating 5 MTD partitions on "spi0.0": 382 # 0x000000000000-0x000000040000 : "u-boot" 383 # 0x000000040000-0x000000fa0000 : "firmware" 384 # 2 uimage-fw partitions found on MTD device firmware 385 # Creating 2 MTD partitions on "firmware": 386 # 0x000000000000-0x0000002c0000 : "kernel" 387 # 0x0000002c0000-0x000000f60000 : "rootfs" 388 # mtd: setting mtd3 (rootfs) as root device 389 # 1 squashfs-split partitions found on MTD device rootfs 390 # 0x000000640000-0x000000f60000 : "rootfs_data" 391 # 0x000000fa0000-0x000000fb0000 : "config" 392 # 0x000000fb0000-0x000000ff0000 : "tplink" 393 # 0x000000ff0000-0x000001000000 : "radio" 394 flash = { 395 # from the OEM bootlog 'Booting image at bc040000' 396 # (0x40000 from 0xbc000000) 397 address = lim.parseInt "0xbc040000"; 398 # 0x000000040000-0x000000fa0000 399 size = lim.parseInt "0xf60000"; 400 # TODO: find in /proc/mtd on a running system 401 eraseBlockSize = 65536; 402 }; 403 404 # since this is mentioned in the partition table as well? 405 defaultOutput = "tplink-safeloader"; 406 # taken from openwrt sysupgrade image: 407 # openwrt-23.05.2-ramips-mt7621-tplink_archer-ax23-v1-squashfs-sysupgrade.bin: u-boot legacy uImage, MIPS OpenWrt Linux-5.15.137, Linux/MIPS, OS Kernel Image (lzma), 2797386 bytes, Tue Nov 14 13:38:11 2023, Load Address: 0X80001000, Entry Point: 0X80001000, Header CRC: 0X19F74C5B, Data CRC: 0XF685563C 408 loadAddress = lim.parseInt "0x80001000"; 409 entryPoint = lim.parseInt "0x80001000"; 410 rootDevice = "/dev/mtdblock3"; 411 dts = { 412 src = "${openwrt.src}/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts"; 413 includes = [ 414 "${openwrt.src}/target/linux/ramips/dts" 415 "${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/" 416 ]; 417 }; 418 419 networkInterfaces = 420 let 421 inherit (config.system.service.network) link; 422 inherit (config.system.service) bridge; 423 in rec { 424 lan1 = link.build { ifname = "lan1"; }; 425 lan2 = link.build { ifname = "lan2"; }; 426 lan3 = link.build { ifname = "lan3"; }; 427 lan4 = link.build { ifname = "lan4"; }; 428 wan = link.build { ifname = "wan"; }; 429 430 wlan = link.build { 431 ifname = "wlan0"; 432 dependencies = [ mac80211 ]; 433 }; 434 wlan5 = link.build { 435 ifname = "wlan1"; 436 dependencies = [ mac80211 ]; 437 }; 438 }; 439 }; 440 }; 441 }; 442 }