default.nix (27275B)
1 { 2 description = '' 3 OpenWrt One 4 *********** 5 6 Hardware summary 7 ================ 8 9 - MediaTek MT7981B (1300MHz) 10 - 256MB NAND Flash 11 - 1024MB RAM 12 - WLan hardware: Mediatek MT7976C 13 14 Status 15 ====== 16 17 - Only tested over TFTP so far. 18 - WiFi (2.4G and 5G) works. 19 - 2.5G ethernet port works. 20 21 Limitations 22 =========== 23 24 - adding `he_bss_color="128"` causes `Invalid argument` for hostap 25 - nvme support untested 26 - I don't think the front LEDs work yet 27 28 Installation 29 ============ 30 31 TODO: add instructions on how to boot directly from TFTP to memory 32 and how to install from TFTP to flash without going through OpenWrt. 33 34 The instructions below assume you can boot and SSH into OpenWrt: 35 36 Boot into OpenWrt and create a 'liminix' UBI partition: 37 38 root@OpenWrt:~# ubimkvol /dev/ubi0 --name=liminix --maxavsize 39 40 Remember the 'Volume ID' that was created for this new partition 41 42 Build the UBI image and write it to this new partition: 43 44 $ nix-build -I liminix-config=./my-configuration.nix --arg device "import ./devices/openwrt-one" -A outputs.default 45 $ cat result/rootfs | ssh root@192.168.1.1 "cat > /tmp/rootfs" 46 $ ssh root@192.168.1.1 47 root@OpenWrt:~# ubiupdatevol /dev/ubi0_X /tmp/rootfs # replace X with the volume id, if needed check with `ubinfo` 48 49 Reboot into the U-Boot prompt and boot with: 50 51 OpenWrt One> ubifsmount ubi0:liminix && ubifsload ''${loadaddr} boot/fit && bootm ''${loadaddr}' 52 53 If this works, reboot into OpenWrt and configure U-Boot to boot ubifs by default: 54 55 root@OpenWrt:~# fw_setenv orig_boot_production $(fw_printenv -n boot_production) 56 root@OpenWrt:~# fw_setenv boot_production 'led white on ; ubifsmount ubi0:liminix && ubifsload ''${loadaddr} boot/fit && bootm ''${loadaddr}' 57 58 Troubleshooting 59 =============== 60 61 The instructions above assume you can boot and SSH into the (recovery) 62 OpenWrt installation. If you have broken your device to the point where that 63 is no longer possible, you could re-install OpenWrt, but probably you could 64 also install directly from U-Boot: 65 66 https://github.com/u-boot/u-boot/blob/master/doc/README.ubi 67 ''; 68 69 system = { 70 crossSystem = { 71 config = "aarch64-unknown-linux-musl"; 72 gcc = { 73 # https://openwrt.org/docs/techref/instructionset/aarch64_cortex-a53 74 # openwrt ./target/linux/mediatek/filogic/target.mk 75 # https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html 76 # https://en.wikipedia.org/wiki/Comparison_of_ARM_processors 77 arch = "armv8-a"; 78 }; 79 }; 80 }; 81 82 module = 83 { 84 pkgs, 85 config, 86 lib, 87 lim, 88 ... 89 }: 90 let 91 openwrt = pkgs.openwrt_24_10; 92 mediatek-firmware = pkgs.stdenv.mkDerivation { 93 name = "wlan-firmware"; 94 phases = [ "installPhase" ]; 95 installPhase = '' 96 mkdir $out 97 98 cp ${pkgs.linux-firmware}/lib/firmware/mediatek/{mt7915,mt7615,mt7986_eeprom_mt7976,mt7981}* $out 99 ''; 100 }; 101 airoha-firmware = pkgs.stdenv.mkDerivation { 102 name = "airoha-firmware"; 103 phases = [ "installPhase" ]; 104 installPhase = '' 105 mkdir $out 106 107 cp ${pkgs.linux-firmware}/lib/firmware/airoha/* $out 108 ''; 109 }; 110 in 111 { 112 imports = [ 113 ../../modules/arch/aarch64.nix 114 ../../modules/outputs/tftpboot.nix 115 ../../modules/outputs/ubifs.nix 116 ]; 117 config = { 118 kernel = { 119 src = openwrt.kernelSrc; 120 version = openwrt.kernelVersion; 121 extraPatchPhase = '' 122 ${openwrt.applyPatches.mediatek} 123 ''; 124 config = 125 { 126 NET = "y"; # unlock NET_XGRESS 127 SERIAL_8250 = "y"; # unlock SERIAL_8250_FSL 128 SERIAL_8250_CONSOLE = "y"; # to get the serial console 129 WATCHDOG = "y"; # unlock WATCHDOG_CORE 130 NEW_LEDS = "y"; # unlock LEDS_PWM 131 LEDS_CLASS = "y"; # unlock LEDS_PWM 132 LEDS_TRIGGERS = "y"; # unlock LEDS_TRIGGER_PATTERN 133 DEFERRED_STRUCT_PAGE_INIT = "y"; # trigger PADATA 134 # Taken from openwrt's ./target/linux/mediatek/filogic/config-6.6 135 "64BIT" = "y"; 136 AIROHA_EN8801SC_PHY = "y"; 137 ARCH_BINFMT_ELF_EXTRA_PHDRS = "y"; 138 ARCH_CORRECT_STACKTRACE_ON_KRETPROBE = "y"; 139 ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG = "y"; 140 ARCH_DMA_ADDR_T_64BIT = "y"; 141 ARCH_FORCE_MAX_ORDER = "10"; 142 ARCH_KEEP_MEMBLOCK = "y"; 143 ARCH_MEDIATEK = "y"; 144 ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE = "y"; 145 ARCH_MMAP_RND_BITS = "18"; 146 ARCH_MMAP_RND_BITS_MAX = "24"; 147 ARCH_MMAP_RND_BITS_MIN = "18"; 148 ARCH_MMAP_RND_COMPAT_BITS_MIN = "11"; 149 ARCH_PROC_KCORE_TEXT = "y"; 150 ARCH_SPARSEMEM_ENABLE = "y"; 151 ARCH_STACKWALK = "y"; 152 ARCH_SUSPEND_POSSIBLE = "y"; 153 ARCH_WANTS_NO_INSTR = "y"; 154 ARCH_WANTS_THP_SWAP = "y"; 155 ARM64 = "y"; 156 ARM64_4K_PAGES = "y"; 157 ARM64_ERRATUM_843419 = "y"; 158 ARM64_LD_HAS_FIX_ERRATUM_843419 = "y"; 159 ARM64_PAGE_SHIFT = "12"; 160 ARM64_PA_BITS = "48"; 161 ARM64_PA_BITS_48 = "y"; 162 ARM64_TAGGED_ADDR_ABI = "y"; 163 ARM64_VA_BITS = "39"; 164 ARM64_VA_BITS_39 = "y"; 165 ARM_AMBA = "y"; 166 ARM_ARCH_TIMER = "y"; 167 ARM_ARCH_TIMER_EVTSTREAM = "y"; 168 ARM_GIC = "y"; 169 ARM_GIC_V2M = "y"; 170 ARM_GIC_V3 = "y"; 171 ARM_GIC_V3_ITS = "y"; 172 ARM_GIC_V3_ITS_PCI = "y"; 173 ARM_MEDIATEK_CPUFREQ = "y"; 174 ARM_PMU = "y"; 175 ARM_PMUV3 = "y"; 176 ARM_PSCI_FW = "y"; 177 ATA = "y"; 178 AUDIT_ARCH_COMPAT_GENERIC = "y"; 179 BLK_DEV_LOOP = "y"; 180 BLK_DEV_SD = "y"; 181 BLK_MQ_PCI = "y"; 182 BLK_PM = "y"; 183 BLOCK_NOTIFIERS = "y"; 184 BSD_PROCESS_ACCT = "y"; 185 BSD_PROCESS_ACCT_V3 = "y"; 186 BUFFER_HEAD = "y"; 187 BUILTIN_RETURN_ADDRESS_STRIPS_PAC = "y"; 188 CC_HAVE_SHADOW_CALL_STACK = "y"; 189 CC_HAVE_STACKPROTECTOR_SYSREG = "y"; 190 #CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"; 191 CC_NO_ARRAY_BOUNDS = "y"; 192 CLKSRC_MMIO = "y"; 193 CLONE_BACKWARDS = "y"; 194 CMDLINE_OVERRIDE = "y"; 195 COMMON_CLK = "y"; 196 COMMON_CLK_MEDIATEK = "y"; 197 COMMON_CLK_MT7981 = "y"; 198 COMMON_CLK_MT7981_ETHSYS = "y"; 199 COMMON_CLK_MT7986 = "y"; 200 COMMON_CLK_MT7986_ETHSYS = "y"; 201 COMMON_CLK_MT7988 = "y"; 202 COMPACT_UNEVICTABLE_DEFAULT = "1"; 203 CONFIGFS_FS = "y"; 204 CONSOLE_LOGLEVEL_DEFAULT = "15"; 205 CONTEXT_TRACKING = "y"; 206 CONTEXT_TRACKING_IDLE = "y"; 207 CPU_FREQ = "y"; 208 CPU_FREQ_DEFAULT_GOV_USERSPACE = "y"; 209 CPU_FREQ_GOV_ATTR_SET = "y"; 210 CPU_FREQ_GOV_COMMON = "y"; 211 CPU_FREQ_GOV_CONSERVATIVE = "y"; 212 CPU_FREQ_GOV_ONDEMAND = "y"; 213 CPU_FREQ_GOV_PERFORMANCE = "y"; 214 CPU_FREQ_GOV_POWERSAVE = "y"; 215 CPU_FREQ_GOV_SCHEDUTIL = "y"; 216 CPU_FREQ_GOV_USERSPACE = "y"; 217 CPU_FREQ_STAT = "y"; 218 CPU_LITTLE_ENDIAN = "y"; 219 CPU_RMAP = "y"; 220 CPU_THERMAL = "y"; 221 CRC16 = "y"; 222 CRC_CCITT = "y"; 223 CRYPTO_AES_ARM64 = "y"; 224 CRYPTO_AES_ARM64_CE = "y"; 225 CRYPTO_AES_ARM64_CE_BLK = "y"; 226 CRYPTO_AES_ARM64_CE_CCM = "y"; 227 CRYPTO_CMAC = "y"; 228 CRYPTO_CRC32 = "y"; 229 CRYPTO_CRC32C = "y"; 230 CRYPTO_CRYPTD = "y"; 231 CRYPTO_DEFLATE = "y"; 232 CRYPTO_DRBG = "y"; 233 CRYPTO_DRBG_HMAC = "y"; 234 CRYPTO_DRBG_MENU = "y"; 235 CRYPTO_ECB = "y"; 236 CRYPTO_ECC = "y"; 237 CRYPTO_ECDH = "y"; 238 CRYPTO_GHASH_ARM64_CE = "y"; 239 CRYPTO_HASH_INFO = "y"; 240 CRYPTO_HMAC = "y"; 241 CRYPTO_JITTERENTROPY = "y"; 242 CRYPTO_LIB_BLAKE2S_GENERIC = "y"; 243 CRYPTO_LIB_GF128MUL = "y"; 244 CRYPTO_LIB_SHA1 = "y"; 245 CRYPTO_LIB_SHA256 = "y"; 246 CRYPTO_LIB_UTILS = "y"; 247 CRYPTO_LZO = "y"; 248 CRYPTO_RNG = "y"; 249 CRYPTO_RNG2 = "y"; 250 CRYPTO_RNG_DEFAULT = "y"; 251 CRYPTO_SHA256 = "y"; 252 CRYPTO_SHA256_ARM64 = "y"; 253 CRYPTO_SHA2_ARM64_CE = "y"; 254 CRYPTO_SHA3 = "y"; 255 CRYPTO_SHA512 = "y"; 256 CRYPTO_SM4 = "y"; 257 CRYPTO_SM4_ARM64_CE_BLK = "y"; 258 CRYPTO_SM4_ARM64_CE_CCM = "y"; 259 CRYPTO_SM4_ARM64_CE_GCM = "y"; 260 CRYPTO_ZSTD = "y"; 261 DCACHE_WORD_ACCESS = "y"; 262 #DEBUG_INFO="y"; 263 DEBUG_MISC = "y"; 264 DIMLIB = "y"; 265 DMADEVICES = "y"; 266 DMATEST = "y"; 267 DMA_BOUNCE_UNALIGNED_KMALLOC = "y"; 268 DMA_DIRECT_REMAP = "y"; 269 DMA_ENGINE = "y"; 270 DMA_ENGINE_RAID = "y"; 271 DMA_OF = "y"; 272 DMA_VIRTUAL_CHANNELS = "y"; 273 DTC = "y"; 274 EDAC_SUPPORT = "y"; 275 EINT_MTK = "y"; 276 EXCLUSIVE_SYSTEM_RAM = "y"; 277 EXT4_FS = "y"; 278 F2FS_FS = "y"; 279 FIXED_PHY = "y"; 280 FIX_EARLYCON_MEM = "y"; 281 FRAME_POINTER = "y"; 282 FS_IOMAP = "y"; 283 FS_MBCACHE = "y"; 284 FUNCTION_ALIGNMENT = "4"; 285 FUNCTION_ALIGNMENT_4B = "y"; 286 FWNODE_MDIO = "y"; 287 FW_LOADER_PAGED_BUF = "y"; 288 #FW_LOADER_SYSFS="y"; 289 #GCC11_NO_ARRAY_BOUNDS="y"; 290 #GCC_ASM_GOTO_OUTPUT_WORKAROUND="y"; 291 GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS = "y"; 292 GENERIC_ALLOCATOR = "y"; 293 GENERIC_ARCH_TOPOLOGY = "y"; 294 GENERIC_BUG = "y"; 295 GENERIC_BUG_RELATIVE_POINTERS = "y"; 296 GENERIC_CLOCKEVENTS = "y"; 297 GENERIC_CLOCKEVENTS_BROADCAST = "y"; 298 GENERIC_CPU_AUTOPROBE = "y"; 299 GENERIC_CPU_VULNERABILITIES = "y"; 300 GENERIC_CSUM = "y"; 301 GENERIC_EARLY_IOREMAP = "y"; 302 GENERIC_GETTIMEOFDAY = "y"; 303 GENERIC_IDLE_POLL_SETUP = "y"; 304 GENERIC_IOREMAP = "y"; 305 GENERIC_IRQ_EFFECTIVE_AFF_MASK = "y"; 306 GENERIC_IRQ_SHOW = "y"; 307 GENERIC_IRQ_SHOW_LEVEL = "y"; 308 GENERIC_LIB_DEVMEM_IS_ALLOWED = "y"; 309 GENERIC_MSI_IRQ = "y"; 310 GENERIC_PCI_IOMAP = "y"; 311 GENERIC_PHY = "y"; 312 GENERIC_PINCONF = "y"; 313 GENERIC_PINCTRL_GROUPS = "y"; 314 GENERIC_PINMUX_FUNCTIONS = "y"; 315 GENERIC_SCHED_CLOCK = "y"; 316 GENERIC_SMP_IDLE_THREAD = "y"; 317 GENERIC_STRNCPY_FROM_USER = "y"; 318 GENERIC_STRNLEN_USER = "y"; 319 GENERIC_TIME_VSYSCALL = "y"; 320 GLOB = "y"; 321 GPIO_CDEV = "y"; 322 GPIO_WATCHDOG = "y"; 323 GPIO_WATCHDOG_ARCH_INITCALL = "y"; 324 GRO_CELLS = "y"; 325 HARDIRQS_SW_RESEND = "y"; 326 HAS_DMA = "y"; 327 HAS_IOMEM = "y"; 328 HAS_IOPORT = "y"; 329 HAS_IOPORT_MAP = "y"; 330 HWMON = "y"; 331 HW_RANDOM = "y"; 332 HW_RANDOM_MTK = "y"; 333 I2C = "y"; 334 I2C_BOARDINFO = "y"; 335 I2C_CHARDEV = "y"; 336 I2C_MT65XX = "y"; 337 ICPLUS_PHY = "y"; 338 ILLEGAL_POINTER_VALUE = "0xdead000000000000"; 339 #INITRAMFS_SOURCE=""""; 340 IRQCHIP = "y"; 341 IRQ_DOMAIN = "y"; 342 IRQ_DOMAIN_HIERARCHY = "y"; 343 IRQ_FORCED_THREADING = "y"; 344 IRQ_TIME_ACCOUNTING = "y"; 345 IRQ_WORK = "y"; 346 JBD2 = "y"; 347 JUMP_LABEL = "y"; 348 LEDS_PWM = "y"; 349 LEDS_SMARTRG_LED = "y"; 350 LIBFDT = "y"; 351 LOCK_DEBUGGING_SUPPORT = "y"; 352 LOCK_SPIN_ON_OWNER = "y"; 353 LZO_COMPRESS = "y"; 354 LZO_DECOMPRESS = "y"; 355 MAGIC_SYSRQ = "y"; 356 MAXLINEAR_GPHY = "y"; 357 MDIO_BUS = "y"; 358 MDIO_DEVICE = "y"; 359 MDIO_DEVRES = "y"; 360 MEDIATEK_2P5GE_PHY = "y"; 361 MEDIATEK_GE_PHY = "y"; 362 MEDIATEK_GE_SOC_PHY = "y"; 363 MEDIATEK_WATCHDOG = "y"; 364 MESSAGE_LOGLEVEL_DEFAULT = "7"; 365 MFD_SYSCON = "y"; 366 MIGRATION = "y"; 367 MMC = "y"; 368 MMC_BLOCK = "y"; 369 MMC_CQHCI = "y"; 370 MMC_MTK = "y"; 371 MMU_LAZY_TLB_REFCOUNT = "y"; 372 MODULES_TREE_LOOKUP = "y"; 373 MODULES_USE_ELF_RELA = "y"; 374 MTD_NAND_CORE = "y"; 375 MTD_NAND_ECC = "y"; 376 MTD_NAND_ECC_MEDIATEK = "y"; 377 MTD_NAND_ECC_SW_HAMMING = "y"; 378 MTD_NAND_MTK = "y"; 379 MTD_NAND_MTK_BMT = "y"; 380 MTD_PARSER_TRX = "y"; 381 MTD_RAW_NAND = "y"; 382 MTD_SPI_NAND = "y"; 383 MTD_SPI_NOR = "y"; 384 MTD_SPLIT_FIRMWARE = "y"; 385 MTD_SPLIT_FIT_FW = "y"; 386 MTD_UBI = "y"; 387 MTD_UBI_BEB_LIMIT = "20"; 388 MTD_UBI_BLOCK = "y"; 389 MTD_UBI_FASTMAP = "y"; 390 MTD_UBI_NVMEM = "y"; 391 MTD_UBI_WL_THRESHOLD = "4096"; 392 MTK_CPUX_TIMER = "y"; 393 MTK_HSDMA = "y"; 394 MTK_INFRACFG = "y"; 395 MTK_LVTS_THERMAL = "y"; 396 MTK_LVTS_THERMAL_DEBUGFS = "y"; 397 MTK_PMIC_WRAP = "y"; 398 MTK_REGULATOR_COUPLER = "y"; 399 MTK_SCPSYS = "y"; 400 MTK_SCPSYS_PM_DOMAINS = "y"; 401 MTK_SOC_THERMAL = "y"; 402 MTK_THERMAL = "y"; 403 MTK_TIMER = "y"; 404 MUTEX_SPIN_ON_OWNER = "y"; 405 NEED_DMA_MAP_STATE = "y"; 406 NEED_SG_DMA_LENGTH = "y"; 407 NET_DEVLINK = "y"; 408 NET_DSA = "y"; 409 NET_DSA_MT7530 = "y"; 410 NET_DSA_MT7530_MDIO = "y"; 411 NET_DSA_MT7530_MMIO = "y"; 412 NET_DSA_TAG_MTK = "y"; 413 #NET_EGRESS="y"; 414 NET_FLOW_LIMIT = "y"; 415 #NET_INGRESS="y"; 416 NET_MEDIATEK_SOC = "y"; 417 NET_MEDIATEK_SOC_WED = "y"; 418 NET_SELFTESTS = "y"; 419 NET_SWITCHDEV = "y"; 420 NET_VENDOR_MEDIATEK = "y"; 421 #NET_XGRESS="y"; 422 NLS = "y"; 423 NO_HZ_COMMON = "y"; 424 NO_HZ_IDLE = "y"; 425 NR_CPUS = "4"; 426 NVMEM = "y"; 427 NVMEM_BLOCK = "y"; 428 NVMEM_LAYOUTS = "y"; 429 NVMEM_LAYOUT_ADTRAN = "y"; 430 NVMEM_MTK_EFUSE = "y"; 431 NVMEM_SYSFS = "y"; 432 OF = "y"; 433 OF_ADDRESS = "y"; 434 OF_DYNAMIC = "y"; 435 OF_EARLY_FLATTREE = "y"; 436 OF_FLATTREE = "y"; 437 OF_GPIO = "y"; 438 OF_IRQ = "y"; 439 OF_KOBJ = "y"; 440 OF_MDIO = "y"; 441 OF_OVERLAY = "y"; 442 OF_RESOLVE = "y"; 443 PADATA = "y"; 444 PAGE_POOL = "y"; 445 PAGE_POOL_STATS = "y"; 446 PAGE_SIZE_LESS_THAN_256KB = "y"; 447 PAGE_SIZE_LESS_THAN_64KB = "y"; 448 #PAHOLE_HAS_LANG_EXCLUDE="y"; 449 PARTITION_PERCPU = "y"; 450 PCI = "y"; 451 PCIEAER = "y"; 452 PCIEASPM = "y"; 453 PCIEASPM_PERFORMANCE = "y"; 454 PCIEPORTBUS = "y"; 455 PCIE_MEDIATEK_GEN3 = "y"; 456 PCIE_PME = "y"; 457 PCI_DEBUG = "y"; 458 PCI_DOMAINS = "y"; 459 PCI_DOMAINS_GENERIC = "y"; 460 PCI_MSI = "y"; 461 PCS_MTK_LYNXI = "y"; 462 PCS_MTK_USXGMII = "y"; 463 PERF_EVENTS = "y"; 464 PER_VMA_LOCK = "y"; 465 PGTABLE_LEVELS = "3"; 466 PHYLIB = "y"; 467 PHYLIB_LEDS = "y"; 468 PHYLINK = "y"; 469 PHYS_ADDR_T_64BIT = "y"; 470 PHY_MTK_TPHY = "y"; 471 PHY_MTK_XFI_TPHY = "y"; 472 PHY_MTK_XSPHY = "y"; 473 PINCTRL = "y"; 474 PINCTRL_MT7981 = "y"; 475 PINCTRL_MT7986 = "y"; 476 PINCTRL_MT7988 = "y"; 477 PINCTRL_MTK_MOORE = "y"; 478 PINCTRL_MTK_V2 = "y"; 479 PM = "y"; 480 PM_CLK = "y"; 481 PM_GENERIC_DOMAINS = "y"; 482 PM_GENERIC_DOMAINS_OF = "y"; 483 PM_OPP = "y"; 484 POLYNOMIAL = "y"; 485 POSIX_CPU_TIMERS_TASK_WORK = "y"; 486 POWER_RESET = "y"; 487 POWER_RESET_SYSCON = "y"; 488 POWER_SUPPLY = "y"; 489 PREEMPT_NONE_BUILD = "y"; 490 PRINTK_TIME = "y"; 491 PSTORE = "y"; 492 PSTORE_COMPRESS = "y"; 493 PSTORE_CONSOLE = "y"; 494 PSTORE_PMSG = "y"; 495 PSTORE_RAM = "y"; 496 PTP_1588_CLOCK_OPTIONAL = "y"; 497 PWM = "y"; 498 PWM_MEDIATEK = "y"; 499 PWM_SYSFS = "y"; 500 QUEUED_RWLOCKS = "y"; 501 QUEUED_SPINLOCKS = "y"; 502 RANDSTRUCT_NONE = "y"; 503 RAS = "y"; 504 RATIONAL = "y"; 505 REALTEK_PHY = "y"; 506 REED_SOLOMON = "y"; 507 REED_SOLOMON_DEC8 = "y"; 508 REED_SOLOMON_ENC8 = "y"; 509 REGMAP = "y"; 510 REGMAP_I2C = "y"; 511 REGMAP_MMIO = "y"; 512 REGULATOR = "y"; 513 REGULATOR_FIXED_VOLTAGE = "y"; 514 REGULATOR_MT6380 = "y"; 515 REGULATOR_RT5190A = "y"; 516 RESET_CONTROLLER = "y"; 517 RESET_TI_SYSCON = "y"; 518 RFS_ACCEL = "y"; 519 RODATA_FULL_DEFAULT_ENABLED = "y"; 520 RPS = "y"; 521 RTC_CLASS = "y"; 522 RTC_DRV_MT7622 = "y"; 523 RTC_I2C_AND_SPI = "y"; 524 RWSEM_SPIN_ON_OWNER = "y"; 525 SCHED_MC = "y"; 526 SCSI = "y"; 527 SCSI_COMMON = "y"; 528 SERIAL_8250_FSL = "y"; 529 SERIAL_8250_MT6577 = "y"; 530 SERIAL_8250_NR_UARTS = "3"; 531 SERIAL_8250_RUNTIME_UARTS = "3"; 532 SERIAL_DEV_BUS = "y"; 533 SERIAL_DEV_CTRL_TTYPORT = "y"; 534 SERIAL_MCTRL_GPIO = "y"; 535 SERIAL_OF_PLATFORM = "y"; 536 SGL_ALLOC = "y"; 537 SG_POOL = "y"; 538 SMP = "y"; 539 SOCK_RX_QUEUE_MAPPING = "y"; 540 SOFTIRQ_ON_OWN_STACK = "y"; 541 SPARSEMEM = "y"; 542 SPARSEMEM_EXTREME = "y"; 543 SPARSEMEM_VMEMMAP = "y"; 544 SPARSEMEM_VMEMMAP_ENABLE = "y"; 545 SPARSE_IRQ = "y"; 546 SPI = "y"; 547 SPI_DYNAMIC = "y"; 548 SPI_MASTER = "y"; 549 SPI_MEM = "y"; 550 SPI_MT65XX = "y"; 551 SPI_MTK_SNFI = "y"; 552 #SQUASHFS_DECOMP_MULTI_PERCPU="y"; 553 SWIOTLB = "y"; 554 SWPHY = "y"; 555 SYSCTL_EXCEPTION_TRACE = "y"; 556 THERMAL = "y"; 557 THERMAL_DEFAULT_GOV_STEP_WISE = "y"; 558 THERMAL_EMERGENCY_POWEROFF_DELAY_MS = "0"; 559 THERMAL_GOV_BANG_BANG = "y"; 560 THERMAL_GOV_FAIR_SHARE = "y"; 561 THERMAL_GOV_STEP_WISE = "y"; 562 THERMAL_GOV_USER_SPACE = "y"; 563 THERMAL_HWMON = "y"; 564 THERMAL_OF = "y"; 565 THERMAL_WRITABLE_TRIPS = "y"; 566 THREAD_INFO_IN_TASK = "y"; 567 TICK_CPU_ACCOUNTING = "y"; 568 TIMER_OF = "y"; 569 TIMER_PROBE = "y"; 570 TRACE_IRQFLAGS_NMI_SUPPORT = "y"; 571 TREE_RCU = "y"; 572 TREE_SRCU = "y"; 573 UBIFS_FS = "y"; 574 UIMAGE_FIT_BLK = "y"; 575 USB_SUPPORT = "y"; 576 VMAP_STACK = "y"; 577 WATCHDOG_CORE = "y"; 578 WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC = "y"; 579 WATCHDOG_PRETIMEOUT_GOV = "y"; 580 WATCHDOG_PRETIMEOUT_GOV_PANIC = "y"; 581 WATCHDOG_PRETIMEOUT_GOV_SEL = "m"; 582 WATCHDOG_SYSFS = "y"; 583 XPS = "y"; 584 XXHASH = "y"; 585 ZLIB_DEFLATE = "y"; 586 ZLIB_INFLATE = "y"; 587 ZONE_DMA32 = "y"; 588 ZSTD_COMMON = "y"; 589 ZSTD_COMPRESS = "y"; 590 ZSTD_DECOMPRESS = "y"; 591 # from DEVICE_PACKAGES in the openwrt_one section of 592 # openwrt's ./target/linux/mediatek/image/filogic.mk: 593 # chop off the 'kmod-' prefix and search for 'KernelPackage/...' 594 # in ./package/kernel/linux/modules/*.mk, and remember to add 595 # modules to kmodloader targets below 596 AIR_EN8811H_PHY = "m"; 597 RTC_DRV_PCF8563 = "m"; 598 NVME_CORE = "m"; 599 BLK_DEV_NVME = "m"; 600 NVME_MULTIPATH = "n"; 601 NVME_HWMON = "y"; 602 # ??? 603 AQUANTIA_PHY = "m"; 604 MT798X_WMAC = "y"; 605 } 606 // lib.optionalAttrs (config.system.service ? watchdog) { 607 RALINK_WDT = "y"; # watchdog 608 MT7621_WDT = "y"; # or it might be this one 609 }; 610 conditionalConfig = { 611 WLAN = { 612 MT7915E = "m"; 613 }; 614 }; 615 }; 616 boot = { 617 commandLine = [ "console=ttyS0,115200" ]; 618 tftp = { 619 # Should be a segment of free RAM, where the tftp artifact 620 # can be stored before unpacking it to the 'hardware.loadAddress' 621 # The 'hardware.loadAddress' is 0x44000000, and the bootlog 622 # suggests it loads the fit to 0x46000000 623 loadAddress = lim.parseInt "0x46000000"; 624 }; 625 imageFormat = "fit"; 626 loader.fit.enable = lib.mkDefault true; # override this if you are building tftpboot 627 }; 628 rootfsType = lib.mkDefault "ubifs"; # override this if you are building tftpboot 629 filesystem = 630 let 631 inherit (pkgs.pseudofile) dir symlink; 632 in 633 dir { 634 lib = dir { 635 firmware = dir { 636 mediatek = symlink mediatek-firmware; 637 airoha = symlink airoha-firmware; 638 }; 639 }; 640 }; 641 642 hardware = 643 let 644 phy = pkgs.kmodloader.override { 645 targets = [ 646 "air_en8811h" 647 ]; 648 inherit (config.system.outputs) kernel; 649 }; 650 mac80211 = pkgs.kmodloader.override { 651 targets = [ 652 "mt7915e" 653 "rtc-pcf8563" 654 "nvme_core" 655 "nvme" 656 #"mt7996e" 657 "aquantia" 658 ]; 659 inherit (config.system.outputs) kernel; 660 }; 661 in 662 { 663 # from OEM bootlog 664 # Creating 4 MTD partitions on "spi0.0": 665 # 0x000000000000-0x000000040000 : "bl2-nor" 666 # 0x000000040000-0x000000100000 : "factory" 667 # 0x000000100000-0x000000180000 : "fip-nor" 668 # 0x000000180000-0x000000e00000 : "recovery" 669 # spi-nand spi1.1: calibration result: 0x3 670 # spi-nand spi1.1: Winbond SPI NAND was found. 671 # spi-nand spi1.1: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128 672 # 2 fixed-partitions partitions found on MTD device spi1.1 673 # Creating 2 MTD partitions on "spi1.1": 674 # 0x000000000000-0x000000100000 : "bl2" 675 # 0x000000100000-0x000010000000 : "ubi" 676 677 flash = { 678 # from the OEM bootlog: 679 # ## Checking Image at 46000000 ... 680 # FIT image found 681 # FIT description: ARM64 OpenWrt FIT (Flattened Image Tree) 682 # Image 0 (kernel-1) 683 # Description: ARM64 OpenWrt Linux-6.6.57 684 # Type: Kernel Image 685 # Compression: gzip compressed 686 # Data Start: 0x46001000 687 # Data Size: 5751840 Bytes = 5.5 MiB 688 # Architecture: AArch64 689 # OS: Linux 690 # Load Address: 0x44000000 691 # Entry Point: 0x44000000 692 693 address = lim.parseInt "0x44000000"; 694 size = lim.parseInt "0xf60000"; 695 # /proc/mtd on a running system: 696 # dev: size erasesize name 697 # mtd0: 00040000 00010000 "bl2-nor" 698 # mtd1: 000c0000 00010000 "factory" 699 # mtd2: 00080000 00010000 "fip-nor" 700 # mtd3: 00c80000 00010000 "recovery" 701 # mtd4: 00100000 00020000 "bl2" 702 # mtd5: 0ff00000 00020000 "ubi" 703 eraseBlockSize = 65536; 704 }; 705 ubi = { 706 # TODO taken from belkin-rt3200, to review 707 minIOSize = "2048"; 708 logicalEraseBlockSize = "126976"; 709 physicalEraseBlockSize = "131072"; 710 maxLEBcount = "1024"; # guessing 711 }; 712 713 defaultOutput = "ubimage"; 714 loadAddress = lim.parseInt "0x44000000"; 715 entryPoint = lim.parseInt "0x44000000"; 716 # TODO AFAICT this should be 2048, but I got 'FIT: image rootfs-1 start not aligned to page boundaries' with that... 717 #alignment = 2048; 718 alignment = 4096; 719 rootDevice = "ubi0:liminix"; 720 dts = { 721 src = "${openwrt.src}/target/linux/mediatek/dts/mt7981b-openwrt-one.dts"; 722 includePaths = [ 723 "${openwrt.src}/target/linux/mediatek/dts" 724 "${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/" 725 ]; 726 }; 727 728 networkInterfaces = 729 let 730 inherit (config.system.service.network) link; 731 in 732 rec { 733 eth0 = link.build { 734 ifname = "eth0"; 735 dependencies = [ phy ]; 736 }; 737 eth1 = link.build { ifname = "eth1"; }; 738 739 wlan0 = link.build { 740 ifname = "wlan0"; 741 dependencies = [ mac80211 ]; 742 }; 743 wlan1 = link.build { 744 ifname = "wlan1"; 745 dependencies = [ mac80211 ]; 746 }; 747 }; 748 }; 749 }; 750 }; 751 }