default.nix (16178B)
1 { 2 description = '' 3 TP-Link Archer AX23 / AX1800 Dual Band Wi-Fi 6 Router 4 ***************************************************** 5 6 Hardware summary 7 ================ 8 9 - MediaTek MT7621 (880MHz) 10 - 16MB Flash 11 - 128MB RAM 12 - WLan hardware: Mediatek MT7905, MT7975 13 14 Limitations 15 =========== 16 17 Status LEDs do not work yet. 18 19 Uploading an image via tftp doesn't work yet, because the Archer uboot 20 version is so old it doesn't support overriding the DTB from the mboot 21 command. The tftpboot module doesn't support this yet, see 22 https://gti.telent.net/dan/liminix/pulls/5 for the WiP. 23 ''; 24 25 system = { 26 crossSystem = { 27 config = "mipsel-unknown-linux-musl"; 28 gcc = { 29 abi = "32"; 30 # https://openwrt.org/docs/techref/instructionset/mipsel_24kc 31 arch = "24kc"; 32 }; 33 }; 34 }; 35 36 module = 37 { 38 pkgs, 39 config, 40 lib, 41 lim, 42 ... 43 }: 44 let 45 firmware = pkgs.stdenv.mkDerivation { 46 name = "wlan-firmware"; 47 phases = [ "installPhase" ]; 48 installPhase = '' 49 mkdir $out 50 cp ${pkgs.linux-firmware}/lib/firmware/mediatek/{mt7915,mt7615,mt7622}* $out 51 ''; 52 }; 53 in 54 { 55 imports = [ 56 ../../modules/arch/mipsel.nix 57 ../../modules/outputs/tftpboot.nix 58 ../../modules/outputs/tplink-safeloader.nix 59 ]; 60 config = { 61 kernel = { 62 extraPatchPhase = '' 63 ${pkgs.openwrt.applyPatches.ramips} 64 ''; 65 config = 66 { 67 # Initially taken from openwrt's ./target/linux/ramips/mt7621/config-5.15, 68 # then tweaked here and there 69 ARCH_32BIT_OFF_T = "y"; 70 ARCH_HIBERNATION_POSSIBLE = "y"; 71 ARCH_KEEP_MEMBLOCK = "y"; 72 ARCH_MMAP_RND_BITS_MAX = "15"; 73 ARCH_MMAP_RND_COMPAT_BITS_MAX = "15"; 74 ARCH_SUSPEND_POSSIBLE = "y"; 75 AT803X_PHY = "y"; 76 BLK_MQ_PCI = "y"; 77 BOARD_SCACHE = "y"; 78 CEVT_R4K = "y"; 79 CLKSRC_MIPS_GIC = "y"; 80 CLK_MT7621 = "y"; 81 CLOCKSOURCE_WATCHDOG = "y"; 82 CLONE_BACKWARDS = "y"; 83 CMDLINE_BOOL = "y"; 84 COMMON_CLK = "y"; 85 COMPAT_32BIT_TIME = "y"; 86 CPU_GENERIC_DUMP_TLB = "y"; 87 CPU_HAS_DIEI = "y"; 88 CPU_HAS_PREFETCH = "y"; 89 CPU_HAS_RIXI = "y"; 90 CPU_HAS_SYNC = "y"; 91 CPU_LITTLE_ENDIAN = "y"; 92 CPU_MIPS32 = "y"; 93 CPU_MIPS32_R2 = "y"; 94 CPU_MIPSR2 = "y"; 95 CPU_MIPSR2_IRQ_EI = "y"; 96 CPU_MIPSR2_IRQ_VI = "y"; 97 CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS = "y"; 98 CPU_R4K_CACHE_TLB = "y"; 99 CPU_RMAP = "y"; 100 CPU_SUPPORTS_32BIT_KERNEL = "y"; 101 CPU_SUPPORTS_HIGHMEM = "y"; 102 CPU_SUPPORTS_MSA = "y"; 103 CRC16 = "y"; 104 CRYPTO_DEFLATE = "y"; 105 CRYPTO_HASH_INFO = "y"; 106 CRYPTO_LIB_BLAKE2S_GENERIC = "y"; 107 CRYPTO_LIB_POLY1305_RSIZE = "2"; 108 CRYPTO_LZO = "y"; 109 CRYPTO_ZSTD = "y"; 110 CSRC_R4K = "y"; 111 DIMLIB = "y"; 112 DMA_NONCOHERENT = "y"; 113 DTB_RT_NONE = "y"; 114 DTC = "y"; 115 EARLY_PRINTK = "y"; 116 FIXED_PHY = "y"; 117 FWNODE_MDIO = "y"; 118 FW_LOADER_PAGED_BUF = "y"; 119 GENERIC_ATOMIC64 = "y"; 120 GENERIC_CLOCKEVENTS = "y"; 121 GENERIC_CMOS_UPDATE = "y"; 122 GENERIC_CPU_AUTOPROBE = "y"; 123 GENERIC_FIND_FIRST_BIT = "y"; 124 GENERIC_GETTIMEOFDAY = "y"; 125 GENERIC_IOMAP = "y"; 126 GENERIC_IRQ_CHIP = "y"; 127 GENERIC_IRQ_EFFECTIVE_AFF_MASK = "y"; 128 GENERIC_IRQ_SHOW = "y"; 129 GENERIC_LIB_ASHLDI3 = "y"; 130 GENERIC_LIB_ASHRDI3 = "y"; 131 GENERIC_LIB_CMPDI2 = "y"; 132 GENERIC_LIB_LSHRDI3 = "y"; 133 GENERIC_LIB_UCMPDI2 = "y"; 134 GENERIC_PCI_IOMAP = "y"; 135 GENERIC_PHY = "y"; 136 GENERIC_PINCONF = "y"; 137 GENERIC_SCHED_CLOCK = "y"; 138 GENERIC_SMP_IDLE_THREAD = "y"; 139 GENERIC_TIME_VSYSCALL = "y"; 140 GLOB = "y"; 141 GPIOLIB_IRQCHIP = "y"; 142 GPIO_CDEV = "y"; 143 GPIO_GENERIC = "y"; 144 GPIO_MT7621 = "y"; 145 GRO_CELLS = "y"; 146 HANDLE_DOMAIN_IRQ = "y"; 147 HARDWARE_WATCHPOINTS = "y"; 148 HAS_DMA = "y"; 149 HAS_IOMEM = "y"; 150 HAS_IOPORT_MAP = "y"; 151 I2C = "y"; 152 I2C_ALGOBIT = "y"; 153 I2C_BOARDINFO = "y"; 154 I2C_CHARDEV = "y"; 155 I2C_GPIO = "y"; 156 I2C_MT7621 = "y"; 157 ICPLUS_PHY = "y"; 158 IRQCHIP = "y"; 159 IRQ_DOMAIN = "y"; 160 IRQ_DOMAIN_HIERARCHY = "y"; 161 IRQ_FORCED_THREADING = "y"; 162 IRQ_MIPS_CPU = "y"; 163 IRQ_WORK = "y"; 164 LIBFDT = "y"; 165 LOCK_DEBUGGING_SUPPORT = "y"; 166 LZO_COMPRESS = "y"; 167 LZO_DECOMPRESS = "y"; 168 MDIO_BUS = "y"; 169 MDIO_DEVICE = "y"; 170 MDIO_DEVRES = "y"; 171 MEDIATEK_GE_PHY = "y"; 172 MEMFD_CREATE = "y"; 173 MFD_SYSCON = "y"; 174 MIGRATION = "y"; 175 MIKROTIK = "y"; 176 MIKROTIK_RB_SYSFS = "y"; 177 MIPS = "y"; 178 MIPS_ASID_BITS = "8"; 179 MIPS_ASID_SHIFT = "0"; 180 MIPS_CLOCK_VSYSCALL = "y"; 181 MIPS_CM = "y"; 182 MIPS_CPC = "y"; 183 MIPS_CPS = "y"; 184 MIPS_CPU_SCACHE = "y"; 185 MIPS_GIC = "y"; 186 MIPS_L1_CACHE_SHIFT = "5"; 187 MIPS_LD_CAN_LINK_VDSO = "y"; 188 MIPS_MT = "y"; 189 MIPS_MT_FPAFF = "y"; 190 MIPS_MT_SMP = "y"; 191 MIPS_NR_CPU_NR_MAP = "4"; 192 MIPS_PERF_SHARED_TC_COUNTERS = "y"; 193 MIPS_SPRAM = "y"; 194 MODULES_USE_ELF_REL = "y"; 195 MTD_CMDLINE_PARTS = "y"; 196 MTD_NAND_CORE = "y"; 197 MTD_NAND_ECC = "y"; 198 MTD_NAND_ECC_SW_HAMMING = "y"; 199 MTD_NAND_MT7621 = "y"; 200 MTD_NAND_MTK_BMT = "y"; 201 MTD_RAW_NAND = "y"; 202 MTD_ROUTERBOOT_PARTS = "y"; 203 MTD_SERCOMM_PARTS = "y"; 204 MTD_SPI_NOR = "y"; 205 MTD_SPLIT_FIT_FW = "y"; 206 MTD_SPLIT_MINOR_FW = "y"; 207 MTD_SPLIT_SEAMA_FW = "y"; 208 MTD_SPLIT_TPLINK_FW = "y"; 209 MTD_SPLIT_TRX_FW = "y"; 210 MTD_SPLIT_UIMAGE_FW = "y"; 211 MTD_UBI = "y"; 212 MTD_UBI_BEB_LIMIT = "20"; 213 MTD_UBI_BLOCK = "y"; 214 MTD_UBI_WL_THRESHOLD = "4096"; 215 MTD_VIRT_CONCAT = "y"; 216 NEED_DMA_MAP_STATE = "y"; 217 NET_DEVLINK = "y"; 218 NET_DSA = "y"; 219 NET_DSA_MT7530 = "y"; 220 NET_DSA_MT7530_MDIO = "y"; 221 NET_DSA_TAG_MTK = "y"; 222 NET_FLOW_LIMIT = "y"; 223 NET_MEDIATEK_SOC = "y"; 224 NET_SELFTESTS = "y"; 225 NET_SWITCHDEV = "y"; 226 NET_VENDOR_MEDIATEK = "y"; 227 NO_HZ_COMMON = "y"; 228 NO_HZ_IDLE = "y"; 229 NR_CPUS = "4"; 230 NVMEM = "y"; 231 OF = "y"; 232 OF_ADDRESS = "y"; 233 OF_EARLY_FLATTREE = "y"; 234 OF_FLATTREE = "y"; 235 OF_GPIO = "y"; 236 OF_IRQ = "y"; 237 OF_KOBJ = "y"; 238 OF_MDIO = "y"; 239 PAGE_POOL = "y"; 240 PAGE_POOL_STATS = "y"; 241 PCI = "y"; 242 PCIE_MT7621 = "y"; 243 PCI_DISABLE_COMMON_QUIRKS = "y"; 244 PCI_DOMAINS = "y"; 245 PCI_DOMAINS_GENERIC = "y"; 246 PCI_DRIVERS_GENERIC = "y"; 247 PCS_MTK_LYNXI = "y"; 248 PERF_USE_VMALLOC = "y"; 249 PGTABLE_LEVELS = "2"; 250 PHYLIB = "y"; 251 PHYLINK = "y"; 252 PHY_MT7621_PCI = "y"; 253 PINCTRL = "y"; 254 PINCTRL_AW9523 = "y"; 255 PINCTRL_MT7621 = "y"; 256 PINCTRL_RALINK = "y"; 257 PINCTRL_SX150X = "y"; 258 POWER_RESET = "y"; 259 POWER_RESET_GPIO = "y"; 260 POWER_SUPPLY = "y"; 261 PTP_1588_CLOCK_OPTIONAL = "y"; 262 QUEUED_RWLOCKS = "y"; 263 QUEUED_SPINLOCKS = "y"; 264 RALINK = "y"; 265 RATIONAL = "y"; 266 REGMAP = "y"; 267 REGMAP_I2C = "y"; 268 REGMAP_MMIO = "y"; 269 REGULATOR = "y"; 270 REGULATOR_FIXED_VOLTAGE = "y"; 271 RESET_CONTROLLER = "y"; 272 RFS_ACCEL = "y"; 273 RPS = "y"; 274 RTC_CLASS = "y"; 275 RTC_DRV_BQ32K = "y"; 276 RTC_DRV_PCF8563 = "y"; 277 RTC_I2C_AND_SPI = "y"; 278 SCHED_SMT = "y"; 279 SERIAL_8250 = "y"; 280 SERIAL_8250_CONSOLE = "y"; 281 SERIAL_8250_NR_UARTS = "3"; 282 SERIAL_8250_RUNTIME_UARTS = "3"; 283 SERIAL_MCTRL_GPIO = "y"; 284 SERIAL_OF_PLATFORM = "y"; 285 SGL_ALLOC = "y"; 286 SMP = "y"; 287 SMP_UP = "y"; 288 SOCK_RX_QUEUE_MAPPING = "y"; 289 SOC_BUS = "y"; 290 SOC_MT7621 = "y"; 291 SPI = "y"; 292 SPI_MASTER = "y"; 293 SPI_MEM = "y"; 294 SPI_MT7621 = "y"; 295 SRCU = "y"; 296 SWPHY = "y"; 297 SYNC_R4K = "y"; 298 SYSCTL_EXCEPTION_TRACE = "y"; 299 SYS_HAS_CPU_MIPS32_R1 = "y"; 300 SYS_HAS_CPU_MIPS32_R2 = "y"; 301 SYS_HAS_EARLY_PRINTK = "y"; 302 SYS_SUPPORTS_32BIT_KERNEL = "y"; 303 SYS_SUPPORTS_ARBIT_HZ = "y"; 304 SYS_SUPPORTS_HIGHMEM = "y"; 305 SYS_SUPPORTS_HOTPLUG_CPU = "y"; 306 SYS_SUPPORTS_LITTLE_ENDIAN = "y"; 307 SYS_SUPPORTS_MIPS16 = "y"; 308 SYS_SUPPORTS_MIPS_CPS = "y"; 309 SYS_SUPPORTS_MULTITHREADING = "y"; 310 SYS_SUPPORTS_SCHED_SMT = "y"; 311 SYS_SUPPORTS_SMP = "y"; 312 SYS_SUPPORTS_ZBOOT = "y"; 313 TARGET_ISA_REV = "2"; 314 TICK_CPU_ACCOUNTING = "y"; 315 TIMER_OF = "y"; 316 TIMER_PROBE = "y"; 317 TREE_RCU = "y"; 318 TREE_SRCU = "y"; 319 UBIFS_FS = "y"; 320 USB_SUPPORT = "y"; 321 USE_OF = "y"; 322 WEAK_ORDERING = "y"; 323 XPS = "y"; 324 XXHASH = "y"; 325 ZLIB_DEFLATE = "y"; 326 ZLIB_INFLATE = "y"; 327 ZSTD_COMPRESS = "y"; 328 ZSTD_DECOMPRESS = "y"; 329 } 330 // lib.optionalAttrs (config.system.service ? watchdog) { 331 RALINK_WDT = "y"; # watchdog 332 MT7621_WDT = "y"; # or it might be this one 333 }; 334 conditionalConfig = { 335 WLAN = { 336 MT7915E = "m"; 337 }; 338 }; 339 }; 340 tplink-safeloader.board = "ARCHER-AX23-V1"; 341 boot = { 342 commandLine = [ "console=ttyS0,115200" ]; 343 tftp = { 344 # Should be a segment of free RAM, where the tftp artifact 345 # can be stored before unpacking it to the 'hardware.loadAddress' 346 # The 'hardware.loadAddress' is 0x80001000, which suggests the 347 # RAM would start at 0x8000000 and (being 128MB) go to 348 # to 0x8800000. Let's put it at the 100MB mark at 349 # 0x8000000+0x0640000=0x86400000 350 loadAddress = lim.parseInt "0x86400000"; 351 }; 352 }; 353 filesystem = 354 let 355 inherit (pkgs.pseudofile) dir symlink; 356 in 357 dir { 358 lib = dir { 359 firmware = dir { 360 mediatek = symlink firmware; 361 }; 362 }; 363 }; 364 365 hardware = 366 let 367 openwrt = pkgs.openwrt; 368 mac80211 = pkgs.kmodloader.override { 369 targets = [ 370 "mt7915e" 371 ]; 372 inherit (config.system.outputs) kernel; 373 }; 374 in 375 { 376 # from OEM bootlog (openwrt wiki): 377 # 4 cmdlinepart partitions found on MTD device raspi 378 # Creating 4 MTD partitions on "raspi": 379 # 0x000000000000-0x000000040000 : "uboot" 380 # 0x000000040000-0x000000440000 : "uImage" 381 # 0x000000440000-0x000000ff0000 : "rootfs" 382 # 0x000000ff0000-0x000001000000 : "ART" 383 # from openwrt bootlog (openwrt wiki): 384 # 5 fixed-partitions partitions found on MTD device spi0.0 385 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 386 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 387 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 388 # OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions 389 # Creating 5 MTD partitions on "spi0.0": 390 # 0x000000000000-0x000000040000 : "u-boot" 391 # 0x000000040000-0x000000fa0000 : "firmware" 392 # 2 uimage-fw partitions found on MTD device firmware 393 # Creating 2 MTD partitions on "firmware": 394 # 0x000000000000-0x0000002c0000 : "kernel" 395 # 0x0000002c0000-0x000000f60000 : "rootfs" 396 # mtd: setting mtd3 (rootfs) as root device 397 # 1 squashfs-split partitions found on MTD device rootfs 398 # 0x000000640000-0x000000f60000 : "rootfs_data" 399 # 0x000000fa0000-0x000000fb0000 : "config" 400 # 0x000000fb0000-0x000000ff0000 : "tplink" 401 # 0x000000ff0000-0x000001000000 : "radio" 402 flash = { 403 # from the OEM bootlog 'Booting image at bc040000' 404 # (0x40000 from 0xbc000000) 405 address = lim.parseInt "0xbc040000"; 406 # 0x000000040000-0x000000fa0000 407 size = lim.parseInt "0xf60000"; 408 # TODO: find in /proc/mtd on a running system 409 eraseBlockSize = 65536; 410 }; 411 412 # since this is mentioned in the partition table as well? 413 defaultOutput = "tplink-safeloader"; 414 # taken from openwrt sysupgrade image: 415 # openwrt-23.05.2-ramips-mt7621-tplink_archer-ax23-v1-squashfs-sysupgrade.bin: u-boot legacy uImage, MIPS OpenWrt Linux-5.15.137, Linux/MIPS, OS Kernel Image (lzma), 2797386 bytes, Tue Nov 14 13:38:11 2023, Load Address: 0X80001000, Entry Point: 0X80001000, Header CRC: 0X19F74C5B, Data CRC: 0XF685563C 416 loadAddress = lim.parseInt "0x80001000"; 417 entryPoint = lim.parseInt "0x80001000"; 418 rootDevice = "/dev/mtdblock3"; 419 dts = { 420 src = "${openwrt.src}/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts"; 421 includePaths = [ 422 "${openwrt.src}/target/linux/ramips/dts" 423 "${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/" 424 ]; 425 }; 426 427 networkInterfaces = 428 let 429 inherit (config.system.service.network) link; 430 in 431 rec { 432 lan1 = link.build { ifname = "lan1"; }; 433 lan2 = link.build { ifname = "lan2"; }; 434 lan3 = link.build { ifname = "lan3"; }; 435 lan4 = link.build { ifname = "lan4"; }; 436 wan = link.build { ifname = "wan"; }; 437 438 wlan = link.build { 439 ifname = "wlan0"; 440 dependencies = [ mac80211 ]; 441 }; 442 wlan5 = link.build { 443 ifname = "wlan1"; 444 dependencies = [ mac80211 ]; 445 }; 446 }; 447 }; 448 }; 449 }; 450 }