eculocate

commit 8ec58c88013a81f8bfb5eaff1448a1185906c06e
parent d05dfc53b4c880eba990971e118ce916a786ccd3
Author: filipton <filipton12@gmail.com>
Date:   Thu,  2 Jan 2025 15:46:23 +0100

wip: port esp32c2

Diffstat:
A
src/mmu_ll/esp32c2.rs
 | 
57
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++
M
src/mmu_ll/mod.rs
 | 
25
+++++++++++++++++++++++++

2 files changed, 82 insertions(+), 0 deletions(-)
diff --git a/src/mmu_ll/esp32c2.rs b/src/mmu_ll/esp32c2.rs
@@ -0,0 +1,57 @@
+use crate::mmu_hal::{MMU_PAGE_16KB, MMU_PAGE_32KB, MMU_PAGE_64KB};
+
+const DR_REG_MMU_TABLE: u32 = 0x600c5000;
+const SOC_MMU_VALID_VAL_MASK: u32 = 0x3f;
+const SOC_MMU_INVALID: u32 = 1 << 6;
+
+fn soc_mmu_vaddr_mask(mmu_id: u32) -> u32 {
+    mmu_ll_get_page_size(mmu_id) * 64 - 1
+}
+
+pub fn mmu_ll_get_page_size(_mmu_id: u32) -> u32 {
+    let extmem = unsafe { &*esp32c2::EXTMEM::ptr() };
+    let cache_mmu_page_size = extmem.cache_conf_misc().read().cache_mmu_page_size().bits();
+    match cache_mmu_page_size {
+        0 => MMU_PAGE_16KB,
+        1 => MMU_PAGE_32KB,
+        _ => MMU_PAGE_64KB,
+    }
+}
+
+pub fn mmu_ll_get_entry_id(mmu_id: u32, vaddr: u32) -> u32 {
+    let shift_code = match mmu_ll_get_page_size(mmu_id) {
+        MMU_PAGE_64KB => 16,
+        MMU_PAGE_32KB => 15,
+        MMU_PAGE_16KB => 14,
+        _ => {
+            #[cfg(feature = "log")]
+            log::error!("mmu_ll_get_entry_id failed!");
+
+            0
+        }
+    };
+
+    (vaddr & soc_mmu_vaddr_mask(mmu_id)) >> shift_code
+}
+
+pub fn mmu_ll_entry_id_to_paddr_base(mmu_id: u32, entry_id: u32) -> u32 {
+    let shift_code = match mmu_ll_get_page_size(mmu_id) {
+        MMU_PAGE_64KB => 16,
+        MMU_PAGE_32KB => 15,
+        MMU_PAGE_16KB => 14,
+        _ => {
+            #[cfg(feature = "log")]
+            log::error!("mmu_ll_entry_id_to_paddr_base failed!");
+
+            0
+        }
+    };
+
+    let ptr = (DR_REG_MMU_TABLE + entry_id * 4) as *const u32;
+    unsafe { ((*ptr) & SOC_MMU_VALID_VAL_MASK) << shift_code }
+}
+
+pub fn mmu_ll_check_entry_valid(_mmu_id: u32, entry_id: u32) -> bool {
+    let ptr = (DR_REG_MMU_TABLE + entry_id * 4) as *const u32;
+    unsafe { ((*ptr) & SOC_MMU_INVALID) == 0 }
+}
diff --git a/src/mmu_ll/mod.rs b/src/mmu_ll/mod.rs
@@ -1,4 +1,29 @@
+#[cfg(feature = "esp32s2")]
+mod esp32s2;
+#[cfg(feature = "esp32s2")]
+pub use esp32s2::*;
+
 #[cfg(feature = "esp32s3")]
 mod esp32s3;
 #[cfg(feature = "esp32s3")]
 pub use esp32s3::*;
+
+#[cfg(feature = "esp32c2")]
+mod esp32c2;
+#[cfg(feature = "esp32c2")]
+pub use esp32c2::*;
+
+#[cfg(feature = "esp32c3")]
+mod esp32c3;
+#[cfg(feature = "esp32c3")]
+pub use esp32c3::*;
+
+#[cfg(feature = "esp32c6")]
+mod esp32c6;
+#[cfg(feature = "esp32c6")]
+pub use esp32c6::*;
+
+#[cfg(feature = "esp32h2")]
+mod esp32h2;
+#[cfg(feature = "esp32h2")]
+pub use esp32h2::*;