2024-12-18 13:17:46 +00:00
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{
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description = ''
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OpenWrt One
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***********
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Hardware summary
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================
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- MediaTek MT7981B (1300MHz)
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- 256MB NAND Flash
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- 1024MB RAM
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- WLan hardware: Mediatek MT7976C
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Status
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======
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- Only tested over TFTP so far.
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- WiFi (2.4G and 5G) works.
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- 2.5G ethernet port works.
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Limitations
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===========
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- adding `he_bss_color="128"` causes `Invalid argument` for hostap
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- nvme support untested
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- I don't think the front LEDs work yet
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Installation
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============
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TODO: add instructions on how to boot directly from TFTP to memory
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and how to install from TFTP to flash without going through OpenWrt.
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The instructions below assume you can boot and SSH into OpenWrt:
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Boot into OpenWrt and create a 'liminix' UBI partition:
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root@OpenWrt:~# ubimkvol /dev/ubi0 --name=liminix --maxavsize
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Remember the 'Volume ID' that was created for this new partition
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Build the UBI image and write it to this new partition:
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$ nix-build -I liminix-config=./my-configuration.nix --arg device "import ./devices/openwrt-one" -A outputs.default
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$ cat result/rootfs | ssh root@192.168.1.1 "cat > /tmp/rootfs"
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$ ssh root@192.168.1.1
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root@OpenWrt:~# ubiupdatevol /dev/ubi0_X /tmp/rootfs # replace X with the volume id, if needed check with `ubinfo`
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Reboot into the U-Boot prompt and boot with:
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OpenWrt One> ubifsmount ubi0:liminix && ubifsload ''${loadaddr} boot/fit && bootm ''${loadaddr}'
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If this works, reboot into OpenWrt and configure U-Boot to boot ubifs by default:
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root@OpenWrt:~# fw_setenv orig_boot_production $(fw_printenv -n boot_production)
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root@OpenWrt:~# fw_setenv boot_production 'led white on ; ubifsmount ubi0:liminix && ubifsload ''${loadaddr} boot/fit && bootm ''${loadaddr}'
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Troubleshooting
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===============
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The instructions above assume you can boot and SSH into the (recovery)
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OpenWrt installation. If you have broken your device to the point where that
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is no longer possible, you could re-install OpenWrt, but probably you could
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also install directly from U-Boot:
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https://github.com/u-boot/u-boot/blob/master/doc/README.ubi
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'';
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system = {
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crossSystem = {
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config = "aarch64-unknown-linux-musl";
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gcc = {
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# https://openwrt.org/docs/techref/instructionset/aarch64_cortex-a53
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# openwrt ./target/linux/mediatek/filogic/target.mk
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# https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html
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# https://en.wikipedia.org/wiki/Comparison_of_ARM_processors
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arch = "armv8-a";
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};
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};
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};
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2025-02-10 21:55:08 +00:00
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module =
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{
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pkgs,
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config,
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lib,
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lim,
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...
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}:
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let
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openwrt = pkgs.openwrt_24_10;
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mediatek-firmware = pkgs.stdenv.mkDerivation {
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name = "wlan-firmware";
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phases = [ "installPhase" ];
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installPhase = ''
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mkdir $out
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cp ${pkgs.linux-firmware}/lib/firmware/mediatek/{mt7915,mt7615,mt7986_eeprom_mt7976,mt7981}* $out
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'';
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};
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airoha-firmware = pkgs.stdenv.mkDerivation {
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name = "airoha-firmware";
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phases = [ "installPhase" ];
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installPhase = ''
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mkdir $out
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cp ${pkgs.linux-firmware}/lib/firmware/airoha/* $out
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'';
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};
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in
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{
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2024-12-18 13:17:46 +00:00
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imports = [
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../../modules/arch/aarch64.nix
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../../modules/outputs/tftpboot.nix
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../../modules/outputs/ubifs.nix
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];
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config = {
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kernel = {
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src = openwrt.kernelSrc;
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version = openwrt.kernelVersion;
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extraPatchPhase = ''
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${openwrt.applyPatches.mediatek}
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'';
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2025-02-10 21:55:08 +00:00
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config =
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{
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NET = "y"; # unlock NET_XGRESS
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SERIAL_8250 = "y"; # unlock SERIAL_8250_FSL
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SERIAL_8250_CONSOLE = "y"; # to get the serial console
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WATCHDOG = "y"; # unlock WATCHDOG_CORE
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NEW_LEDS = "y"; # unlock LEDS_PWM
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LEDS_CLASS = "y"; # unlock LEDS_PWM
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LEDS_TRIGGERS = "y"; # unlock LEDS_TRIGGER_PATTERN
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DEFERRED_STRUCT_PAGE_INIT = "y"; # trigger PADATA
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# Taken from openwrt's ./target/linux/mediatek/filogic/config-6.6
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"64BIT" = "y";
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AIROHA_EN8801SC_PHY = "y";
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ARCH_BINFMT_ELF_EXTRA_PHDRS = "y";
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ARCH_CORRECT_STACKTRACE_ON_KRETPROBE = "y";
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ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG = "y";
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ARCH_DMA_ADDR_T_64BIT = "y";
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ARCH_FORCE_MAX_ORDER = "10";
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ARCH_KEEP_MEMBLOCK = "y";
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ARCH_MEDIATEK = "y";
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ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE = "y";
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ARCH_MMAP_RND_BITS = "18";
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ARCH_MMAP_RND_BITS_MAX = "24";
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ARCH_MMAP_RND_BITS_MIN = "18";
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ARCH_MMAP_RND_COMPAT_BITS_MIN = "11";
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ARCH_PROC_KCORE_TEXT = "y";
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ARCH_SPARSEMEM_ENABLE = "y";
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ARCH_STACKWALK = "y";
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ARCH_SUSPEND_POSSIBLE = "y";
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ARCH_WANTS_NO_INSTR = "y";
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ARCH_WANTS_THP_SWAP = "y";
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ARM64 = "y";
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ARM64_4K_PAGES = "y";
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ARM64_ERRATUM_843419 = "y";
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ARM64_LD_HAS_FIX_ERRATUM_843419 = "y";
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ARM64_PAGE_SHIFT = "12";
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ARM64_PA_BITS = "48";
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ARM64_PA_BITS_48 = "y";
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ARM64_TAGGED_ADDR_ABI = "y";
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ARM64_VA_BITS = "39";
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ARM64_VA_BITS_39 = "y";
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ARM_AMBA = "y";
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ARM_ARCH_TIMER = "y";
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ARM_ARCH_TIMER_EVTSTREAM = "y";
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ARM_GIC = "y";
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ARM_GIC_V2M = "y";
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ARM_GIC_V3 = "y";
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ARM_GIC_V3_ITS = "y";
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ARM_GIC_V3_ITS_PCI = "y";
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ARM_MEDIATEK_CPUFREQ = "y";
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ARM_PMU = "y";
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ARM_PMUV3 = "y";
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ARM_PSCI_FW = "y";
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ATA = "y";
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AUDIT_ARCH_COMPAT_GENERIC = "y";
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BLK_DEV_LOOP = "y";
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BLK_DEV_SD = "y";
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BLK_MQ_PCI = "y";
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BLK_PM = "y";
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BLOCK_NOTIFIERS = "y";
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BSD_PROCESS_ACCT = "y";
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BSD_PROCESS_ACCT_V3 = "y";
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BUFFER_HEAD = "y";
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BUILTIN_RETURN_ADDRESS_STRIPS_PAC = "y";
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CC_HAVE_SHADOW_CALL_STACK = "y";
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CC_HAVE_STACKPROTECTOR_SYSREG = "y";
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#CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5";
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CC_NO_ARRAY_BOUNDS = "y";
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CLKSRC_MMIO = "y";
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CLONE_BACKWARDS = "y";
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CMDLINE_OVERRIDE = "y";
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COMMON_CLK = "y";
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COMMON_CLK_MEDIATEK = "y";
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COMMON_CLK_MT7981 = "y";
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COMMON_CLK_MT7981_ETHSYS = "y";
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COMMON_CLK_MT7986 = "y";
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COMMON_CLK_MT7986_ETHSYS = "y";
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COMMON_CLK_MT7988 = "y";
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COMPACT_UNEVICTABLE_DEFAULT = "1";
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CONFIGFS_FS = "y";
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CONSOLE_LOGLEVEL_DEFAULT = "15";
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CONTEXT_TRACKING = "y";
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CONTEXT_TRACKING_IDLE = "y";
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CPU_FREQ = "y";
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CPU_FREQ_DEFAULT_GOV_USERSPACE = "y";
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CPU_FREQ_GOV_ATTR_SET = "y";
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CPU_FREQ_GOV_COMMON = "y";
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CPU_FREQ_GOV_CONSERVATIVE = "y";
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CPU_FREQ_GOV_ONDEMAND = "y";
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CPU_FREQ_GOV_PERFORMANCE = "y";
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CPU_FREQ_GOV_POWERSAVE = "y";
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CPU_FREQ_GOV_SCHEDUTIL = "y";
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CPU_FREQ_GOV_USERSPACE = "y";
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CPU_FREQ_STAT = "y";
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CPU_LITTLE_ENDIAN = "y";
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CPU_RMAP = "y";
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CPU_THERMAL = "y";
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CRC16 = "y";
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CRC_CCITT = "y";
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CRYPTO_AES_ARM64 = "y";
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CRYPTO_AES_ARM64_CE = "y";
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CRYPTO_AES_ARM64_CE_BLK = "y";
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CRYPTO_AES_ARM64_CE_CCM = "y";
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CRYPTO_CMAC = "y";
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CRYPTO_CRC32 = "y";
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CRYPTO_CRC32C = "y";
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CRYPTO_CRYPTD = "y";
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CRYPTO_DEFLATE = "y";
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CRYPTO_DRBG = "y";
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CRYPTO_DRBG_HMAC = "y";
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CRYPTO_DRBG_MENU = "y";
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CRYPTO_ECB = "y";
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CRYPTO_ECC = "y";
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CRYPTO_ECDH = "y";
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CRYPTO_GHASH_ARM64_CE = "y";
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CRYPTO_HASH_INFO = "y";
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CRYPTO_HMAC = "y";
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CRYPTO_JITTERENTROPY = "y";
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CRYPTO_LIB_BLAKE2S_GENERIC = "y";
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CRYPTO_LIB_GF128MUL = "y";
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CRYPTO_LIB_SHA1 = "y";
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CRYPTO_LIB_SHA256 = "y";
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CRYPTO_LIB_UTILS = "y";
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CRYPTO_LZO = "y";
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CRYPTO_RNG = "y";
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CRYPTO_RNG2 = "y";
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CRYPTO_RNG_DEFAULT = "y";
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CRYPTO_SHA256 = "y";
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CRYPTO_SHA256_ARM64 = "y";
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CRYPTO_SHA2_ARM64_CE = "y";
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CRYPTO_SHA3 = "y";
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CRYPTO_SHA512 = "y";
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CRYPTO_SM4 = "y";
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CRYPTO_SM4_ARM64_CE_BLK = "y";
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CRYPTO_SM4_ARM64_CE_CCM = "y";
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CRYPTO_SM4_ARM64_CE_GCM = "y";
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CRYPTO_ZSTD = "y";
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DCACHE_WORD_ACCESS = "y";
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#DEBUG_INFO="y";
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DEBUG_MISC = "y";
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DIMLIB = "y";
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DMADEVICES = "y";
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DMATEST = "y";
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DMA_BOUNCE_UNALIGNED_KMALLOC = "y";
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DMA_DIRECT_REMAP = "y";
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DMA_ENGINE = "y";
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DMA_ENGINE_RAID = "y";
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DMA_OF = "y";
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DMA_VIRTUAL_CHANNELS = "y";
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DTC = "y";
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EDAC_SUPPORT = "y";
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EINT_MTK = "y";
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EXCLUSIVE_SYSTEM_RAM = "y";
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EXT4_FS = "y";
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F2FS_FS = "y";
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FIXED_PHY = "y";
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FIX_EARLYCON_MEM = "y";
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FRAME_POINTER = "y";
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FS_IOMAP = "y";
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FS_MBCACHE = "y";
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FUNCTION_ALIGNMENT = "4";
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FUNCTION_ALIGNMENT_4B = "y";
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FWNODE_MDIO = "y";
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FW_LOADER_PAGED_BUF = "y";
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#FW_LOADER_SYSFS="y";
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#GCC11_NO_ARRAY_BOUNDS="y";
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#GCC_ASM_GOTO_OUTPUT_WORKAROUND="y";
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GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS = "y";
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GENERIC_ALLOCATOR = "y";
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GENERIC_ARCH_TOPOLOGY = "y";
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GENERIC_BUG = "y";
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GENERIC_BUG_RELATIVE_POINTERS = "y";
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GENERIC_CLOCKEVENTS = "y";
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GENERIC_CLOCKEVENTS_BROADCAST = "y";
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GENERIC_CPU_AUTOPROBE = "y";
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GENERIC_CPU_VULNERABILITIES = "y";
|
|
|
|
|
GENERIC_CSUM = "y";
|
|
|
|
|
GENERIC_EARLY_IOREMAP = "y";
|
|
|
|
|
GENERIC_GETTIMEOFDAY = "y";
|
|
|
|
|
GENERIC_IDLE_POLL_SETUP = "y";
|
|
|
|
|
GENERIC_IOREMAP = "y";
|
|
|
|
|
GENERIC_IRQ_EFFECTIVE_AFF_MASK = "y";
|
|
|
|
|
GENERIC_IRQ_SHOW = "y";
|
|
|
|
|
GENERIC_IRQ_SHOW_LEVEL = "y";
|
|
|
|
|
GENERIC_LIB_DEVMEM_IS_ALLOWED = "y";
|
|
|
|
|
GENERIC_MSI_IRQ = "y";
|
|
|
|
|
GENERIC_PCI_IOMAP = "y";
|
|
|
|
|
GENERIC_PHY = "y";
|
|
|
|
|
GENERIC_PINCONF = "y";
|
|
|
|
|
GENERIC_PINCTRL_GROUPS = "y";
|
|
|
|
|
GENERIC_PINMUX_FUNCTIONS = "y";
|
|
|
|
|
GENERIC_SCHED_CLOCK = "y";
|
|
|
|
|
GENERIC_SMP_IDLE_THREAD = "y";
|
|
|
|
|
GENERIC_STRNCPY_FROM_USER = "y";
|
|
|
|
|
GENERIC_STRNLEN_USER = "y";
|
|
|
|
|
GENERIC_TIME_VSYSCALL = "y";
|
|
|
|
|
GLOB = "y";
|
|
|
|
|
GPIO_CDEV = "y";
|
|
|
|
|
GPIO_WATCHDOG = "y";
|
|
|
|
|
GPIO_WATCHDOG_ARCH_INITCALL = "y";
|
|
|
|
|
GRO_CELLS = "y";
|
|
|
|
|
HARDIRQS_SW_RESEND = "y";
|
|
|
|
|
HAS_DMA = "y";
|
|
|
|
|
HAS_IOMEM = "y";
|
|
|
|
|
HAS_IOPORT = "y";
|
|
|
|
|
HAS_IOPORT_MAP = "y";
|
|
|
|
|
HWMON = "y";
|
|
|
|
|
HW_RANDOM = "y";
|
|
|
|
|
HW_RANDOM_MTK = "y";
|
|
|
|
|
I2C = "y";
|
|
|
|
|
I2C_BOARDINFO = "y";
|
|
|
|
|
I2C_CHARDEV = "y";
|
|
|
|
|
I2C_MT65XX = "y";
|
|
|
|
|
ICPLUS_PHY = "y";
|
|
|
|
|
ILLEGAL_POINTER_VALUE = "0xdead000000000000";
|
|
|
|
|
#INITRAMFS_SOURCE="""";
|
|
|
|
|
IRQCHIP = "y";
|
|
|
|
|
IRQ_DOMAIN = "y";
|
|
|
|
|
IRQ_DOMAIN_HIERARCHY = "y";
|
|
|
|
|
IRQ_FORCED_THREADING = "y";
|
|
|
|
|
IRQ_TIME_ACCOUNTING = "y";
|
|
|
|
|
IRQ_WORK = "y";
|
|
|
|
|
JBD2 = "y";
|
|
|
|
|
JUMP_LABEL = "y";
|
|
|
|
|
LEDS_PWM = "y";
|
|
|
|
|
LEDS_SMARTRG_LED = "y";
|
|
|
|
|
LIBFDT = "y";
|
|
|
|
|
LOCK_DEBUGGING_SUPPORT = "y";
|
|
|
|
|
LOCK_SPIN_ON_OWNER = "y";
|
|
|
|
|
LZO_COMPRESS = "y";
|
|
|
|
|
LZO_DECOMPRESS = "y";
|
|
|
|
|
MAGIC_SYSRQ = "y";
|
|
|
|
|
MAXLINEAR_GPHY = "y";
|
|
|
|
|
MDIO_BUS = "y";
|
|
|
|
|
MDIO_DEVICE = "y";
|
|
|
|
|
MDIO_DEVRES = "y";
|
|
|
|
|
MEDIATEK_2P5GE_PHY = "y";
|
|
|
|
|
MEDIATEK_GE_PHY = "y";
|
|
|
|
|
MEDIATEK_GE_SOC_PHY = "y";
|
|
|
|
|
MEDIATEK_WATCHDOG = "y";
|
|
|
|
|
MESSAGE_LOGLEVEL_DEFAULT = "7";
|
|
|
|
|
MFD_SYSCON = "y";
|
|
|
|
|
MIGRATION = "y";
|
|
|
|
|
MMC = "y";
|
|
|
|
|
MMC_BLOCK = "y";
|
|
|
|
|
MMC_CQHCI = "y";
|
|
|
|
|
MMC_MTK = "y";
|
|
|
|
|
MMU_LAZY_TLB_REFCOUNT = "y";
|
|
|
|
|
MODULES_TREE_LOOKUP = "y";
|
|
|
|
|
MODULES_USE_ELF_RELA = "y";
|
|
|
|
|
MTD_NAND_CORE = "y";
|
|
|
|
|
MTD_NAND_ECC = "y";
|
|
|
|
|
MTD_NAND_ECC_MEDIATEK = "y";
|
|
|
|
|
MTD_NAND_ECC_SW_HAMMING = "y";
|
|
|
|
|
MTD_NAND_MTK = "y";
|
|
|
|
|
MTD_NAND_MTK_BMT = "y";
|
|
|
|
|
MTD_PARSER_TRX = "y";
|
|
|
|
|
MTD_RAW_NAND = "y";
|
|
|
|
|
MTD_SPI_NAND = "y";
|
|
|
|
|
MTD_SPI_NOR = "y";
|
|
|
|
|
MTD_SPLIT_FIRMWARE = "y";
|
|
|
|
|
MTD_SPLIT_FIT_FW = "y";
|
|
|
|
|
MTD_UBI = "y";
|
|
|
|
|
MTD_UBI_BEB_LIMIT = "20";
|
|
|
|
|
MTD_UBI_BLOCK = "y";
|
|
|
|
|
MTD_UBI_FASTMAP = "y";
|
|
|
|
|
MTD_UBI_NVMEM = "y";
|
|
|
|
|
MTD_UBI_WL_THRESHOLD = "4096";
|
|
|
|
|
MTK_CPUX_TIMER = "y";
|
|
|
|
|
MTK_HSDMA = "y";
|
|
|
|
|
MTK_INFRACFG = "y";
|
|
|
|
|
MTK_LVTS_THERMAL = "y";
|
|
|
|
|
MTK_LVTS_THERMAL_DEBUGFS = "y";
|
|
|
|
|
MTK_PMIC_WRAP = "y";
|
|
|
|
|
MTK_REGULATOR_COUPLER = "y";
|
|
|
|
|
MTK_SCPSYS = "y";
|
|
|
|
|
MTK_SCPSYS_PM_DOMAINS = "y";
|
|
|
|
|
MTK_SOC_THERMAL = "y";
|
|
|
|
|
MTK_THERMAL = "y";
|
|
|
|
|
MTK_TIMER = "y";
|
|
|
|
|
MUTEX_SPIN_ON_OWNER = "y";
|
|
|
|
|
NEED_DMA_MAP_STATE = "y";
|
|
|
|
|
NEED_SG_DMA_LENGTH = "y";
|
|
|
|
|
NET_DEVLINK = "y";
|
|
|
|
|
NET_DSA = "y";
|
|
|
|
|
NET_DSA_MT7530 = "y";
|
|
|
|
|
NET_DSA_MT7530_MDIO = "y";
|
|
|
|
|
NET_DSA_MT7530_MMIO = "y";
|
|
|
|
|
NET_DSA_TAG_MTK = "y";
|
|
|
|
|
#NET_EGRESS="y";
|
|
|
|
|
NET_FLOW_LIMIT = "y";
|
|
|
|
|
#NET_INGRESS="y";
|
|
|
|
|
NET_MEDIATEK_SOC = "y";
|
|
|
|
|
NET_MEDIATEK_SOC_WED = "y";
|
|
|
|
|
NET_SELFTESTS = "y";
|
|
|
|
|
NET_SWITCHDEV = "y";
|
|
|
|
|
NET_VENDOR_MEDIATEK = "y";
|
|
|
|
|
#NET_XGRESS="y";
|
|
|
|
|
NLS = "y";
|
|
|
|
|
NO_HZ_COMMON = "y";
|
|
|
|
|
NO_HZ_IDLE = "y";
|
|
|
|
|
NR_CPUS = "4";
|
|
|
|
|
NVMEM = "y";
|
|
|
|
|
NVMEM_BLOCK = "y";
|
|
|
|
|
NVMEM_LAYOUTS = "y";
|
|
|
|
|
NVMEM_LAYOUT_ADTRAN = "y";
|
|
|
|
|
NVMEM_MTK_EFUSE = "y";
|
|
|
|
|
NVMEM_SYSFS = "y";
|
|
|
|
|
OF = "y";
|
|
|
|
|
OF_ADDRESS = "y";
|
|
|
|
|
OF_DYNAMIC = "y";
|
|
|
|
|
OF_EARLY_FLATTREE = "y";
|
|
|
|
|
OF_FLATTREE = "y";
|
|
|
|
|
OF_GPIO = "y";
|
|
|
|
|
OF_IRQ = "y";
|
|
|
|
|
OF_KOBJ = "y";
|
|
|
|
|
OF_MDIO = "y";
|
|
|
|
|
OF_OVERLAY = "y";
|
|
|
|
|
OF_RESOLVE = "y";
|
|
|
|
|
PADATA = "y";
|
|
|
|
|
PAGE_POOL = "y";
|
|
|
|
|
PAGE_POOL_STATS = "y";
|
|
|
|
|
PAGE_SIZE_LESS_THAN_256KB = "y";
|
|
|
|
|
PAGE_SIZE_LESS_THAN_64KB = "y";
|
|
|
|
|
#PAHOLE_HAS_LANG_EXCLUDE="y";
|
|
|
|
|
PARTITION_PERCPU = "y";
|
|
|
|
|
PCI = "y";
|
|
|
|
|
PCIEAER = "y";
|
|
|
|
|
PCIEASPM = "y";
|
|
|
|
|
PCIEASPM_PERFORMANCE = "y";
|
|
|
|
|
PCIEPORTBUS = "y";
|
|
|
|
|
PCIE_MEDIATEK_GEN3 = "y";
|
|
|
|
|
PCIE_PME = "y";
|
|
|
|
|
PCI_DEBUG = "y";
|
|
|
|
|
PCI_DOMAINS = "y";
|
|
|
|
|
PCI_DOMAINS_GENERIC = "y";
|
|
|
|
|
PCI_MSI = "y";
|
|
|
|
|
PCS_MTK_LYNXI = "y";
|
|
|
|
|
PCS_MTK_USXGMII = "y";
|
|
|
|
|
PERF_EVENTS = "y";
|
|
|
|
|
PER_VMA_LOCK = "y";
|
|
|
|
|
PGTABLE_LEVELS = "3";
|
|
|
|
|
PHYLIB = "y";
|
|
|
|
|
PHYLIB_LEDS = "y";
|
|
|
|
|
PHYLINK = "y";
|
|
|
|
|
PHYS_ADDR_T_64BIT = "y";
|
|
|
|
|
PHY_MTK_TPHY = "y";
|
|
|
|
|
PHY_MTK_XFI_TPHY = "y";
|
|
|
|
|
PHY_MTK_XSPHY = "y";
|
|
|
|
|
PINCTRL = "y";
|
|
|
|
|
PINCTRL_MT7981 = "y";
|
|
|
|
|
PINCTRL_MT7986 = "y";
|
|
|
|
|
PINCTRL_MT7988 = "y";
|
|
|
|
|
PINCTRL_MTK_MOORE = "y";
|
|
|
|
|
PINCTRL_MTK_V2 = "y";
|
|
|
|
|
PM = "y";
|
|
|
|
|
PM_CLK = "y";
|
|
|
|
|
PM_GENERIC_DOMAINS = "y";
|
|
|
|
|
PM_GENERIC_DOMAINS_OF = "y";
|
|
|
|
|
PM_OPP = "y";
|
|
|
|
|
POLYNOMIAL = "y";
|
|
|
|
|
POSIX_CPU_TIMERS_TASK_WORK = "y";
|
|
|
|
|
POWER_RESET = "y";
|
|
|
|
|
POWER_RESET_SYSCON = "y";
|
|
|
|
|
POWER_SUPPLY = "y";
|
|
|
|
|
PREEMPT_NONE_BUILD = "y";
|
|
|
|
|
PRINTK_TIME = "y";
|
|
|
|
|
PSTORE = "y";
|
|
|
|
|
PSTORE_COMPRESS = "y";
|
|
|
|
|
PSTORE_CONSOLE = "y";
|
|
|
|
|
PSTORE_PMSG = "y";
|
|
|
|
|
PSTORE_RAM = "y";
|
|
|
|
|
PTP_1588_CLOCK_OPTIONAL = "y";
|
|
|
|
|
PWM = "y";
|
|
|
|
|
PWM_MEDIATEK = "y";
|
|
|
|
|
PWM_SYSFS = "y";
|
|
|
|
|
QUEUED_RWLOCKS = "y";
|
|
|
|
|
QUEUED_SPINLOCKS = "y";
|
|
|
|
|
RANDSTRUCT_NONE = "y";
|
|
|
|
|
RAS = "y";
|
|
|
|
|
RATIONAL = "y";
|
|
|
|
|
REALTEK_PHY = "y";
|
|
|
|
|
REED_SOLOMON = "y";
|
|
|
|
|
REED_SOLOMON_DEC8 = "y";
|
|
|
|
|
REED_SOLOMON_ENC8 = "y";
|
|
|
|
|
REGMAP = "y";
|
|
|
|
|
REGMAP_I2C = "y";
|
|
|
|
|
REGMAP_MMIO = "y";
|
|
|
|
|
REGULATOR = "y";
|
|
|
|
|
REGULATOR_FIXED_VOLTAGE = "y";
|
|
|
|
|
REGULATOR_MT6380 = "y";
|
|
|
|
|
REGULATOR_RT5190A = "y";
|
|
|
|
|
RESET_CONTROLLER = "y";
|
|
|
|
|
RESET_TI_SYSCON = "y";
|
|
|
|
|
RFS_ACCEL = "y";
|
|
|
|
|
RODATA_FULL_DEFAULT_ENABLED = "y";
|
|
|
|
|
RPS = "y";
|
|
|
|
|
RTC_CLASS = "y";
|
|
|
|
|
RTC_DRV_MT7622 = "y";
|
|
|
|
|
RTC_I2C_AND_SPI = "y";
|
|
|
|
|
RWSEM_SPIN_ON_OWNER = "y";
|
|
|
|
|
SCHED_MC = "y";
|
|
|
|
|
SCSI = "y";
|
|
|
|
|
SCSI_COMMON = "y";
|
|
|
|
|
SERIAL_8250_FSL = "y";
|
|
|
|
|
SERIAL_8250_MT6577 = "y";
|
|
|
|
|
SERIAL_8250_NR_UARTS = "3";
|
|
|
|
|
SERIAL_8250_RUNTIME_UARTS = "3";
|
|
|
|
|
SERIAL_DEV_BUS = "y";
|
|
|
|
|
SERIAL_DEV_CTRL_TTYPORT = "y";
|
|
|
|
|
SERIAL_MCTRL_GPIO = "y";
|
|
|
|
|
SERIAL_OF_PLATFORM = "y";
|
|
|
|
|
SGL_ALLOC = "y";
|
|
|
|
|
SG_POOL = "y";
|
|
|
|
|
SMP = "y";
|
|
|
|
|
SOCK_RX_QUEUE_MAPPING = "y";
|
|
|
|
|
SOFTIRQ_ON_OWN_STACK = "y";
|
|
|
|
|
SPARSEMEM = "y";
|
|
|
|
|
SPARSEMEM_EXTREME = "y";
|
|
|
|
|
SPARSEMEM_VMEMMAP = "y";
|
|
|
|
|
SPARSEMEM_VMEMMAP_ENABLE = "y";
|
|
|
|
|
SPARSE_IRQ = "y";
|
|
|
|
|
SPI = "y";
|
|
|
|
|
SPI_DYNAMIC = "y";
|
|
|
|
|
SPI_MASTER = "y";
|
|
|
|
|
SPI_MEM = "y";
|
|
|
|
|
SPI_MT65XX = "y";
|
|
|
|
|
SPI_MTK_SNFI = "y";
|
|
|
|
|
#SQUASHFS_DECOMP_MULTI_PERCPU="y";
|
|
|
|
|
SWIOTLB = "y";
|
|
|
|
|
SWPHY = "y";
|
|
|
|
|
SYSCTL_EXCEPTION_TRACE = "y";
|
|
|
|
|
THERMAL = "y";
|
|
|
|
|
THERMAL_DEFAULT_GOV_STEP_WISE = "y";
|
|
|
|
|
THERMAL_EMERGENCY_POWEROFF_DELAY_MS = "0";
|
|
|
|
|
THERMAL_GOV_BANG_BANG = "y";
|
|
|
|
|
THERMAL_GOV_FAIR_SHARE = "y";
|
|
|
|
|
THERMAL_GOV_STEP_WISE = "y";
|
|
|
|
|
THERMAL_GOV_USER_SPACE = "y";
|
|
|
|
|
THERMAL_HWMON = "y";
|
|
|
|
|
THERMAL_OF = "y";
|
|
|
|
|
THERMAL_WRITABLE_TRIPS = "y";
|
|
|
|
|
THREAD_INFO_IN_TASK = "y";
|
|
|
|
|
TICK_CPU_ACCOUNTING = "y";
|
|
|
|
|
TIMER_OF = "y";
|
|
|
|
|
TIMER_PROBE = "y";
|
|
|
|
|
TRACE_IRQFLAGS_NMI_SUPPORT = "y";
|
|
|
|
|
TREE_RCU = "y";
|
|
|
|
|
TREE_SRCU = "y";
|
|
|
|
|
UBIFS_FS = "y";
|
|
|
|
|
UIMAGE_FIT_BLK = "y";
|
|
|
|
|
USB_SUPPORT = "y";
|
|
|
|
|
VMAP_STACK = "y";
|
|
|
|
|
WATCHDOG_CORE = "y";
|
|
|
|
|
WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC = "y";
|
|
|
|
|
WATCHDOG_PRETIMEOUT_GOV = "y";
|
|
|
|
|
WATCHDOG_PRETIMEOUT_GOV_PANIC = "y";
|
|
|
|
|
WATCHDOG_PRETIMEOUT_GOV_SEL = "m";
|
|
|
|
|
WATCHDOG_SYSFS = "y";
|
|
|
|
|
XPS = "y";
|
|
|
|
|
XXHASH = "y";
|
|
|
|
|
ZLIB_DEFLATE = "y";
|
|
|
|
|
ZLIB_INFLATE = "y";
|
|
|
|
|
ZONE_DMA32 = "y";
|
|
|
|
|
ZSTD_COMMON = "y";
|
|
|
|
|
ZSTD_COMPRESS = "y";
|
|
|
|
|
ZSTD_DECOMPRESS = "y";
|
|
|
|
|
# from DEVICE_PACKAGES in the openwrt_one section of
|
|
|
|
|
# openwrt's ./target/linux/mediatek/image/filogic.mk:
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# chop off the 'kmod-' prefix and search for 'KernelPackage/...'
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# in ./package/kernel/linux/modules/*.mk, and remember to add
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# modules to kmodloader targets below
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AIR_EN8811H_PHY = "m";
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RTC_DRV_PCF8563 = "m";
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NVME_CORE = "m";
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BLK_DEV_NVME = "m";
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NVME_MULTIPATH = "n";
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NVME_HWMON = "y";
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# ???
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AQUANTIA_PHY = "m";
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MT798X_WMAC = "y";
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}
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// lib.optionalAttrs (config.system.service ? watchdog) {
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RALINK_WDT = "y"; # watchdog
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MT7621_WDT = "y"; # or it might be this one
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};
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2024-12-18 13:17:46 +00:00
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conditionalConfig = {
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WLAN = {
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MT7915E = "m";
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};
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};
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};
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boot = {
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commandLine = [ "console=ttyS0,115200" ];
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tftp = {
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# Should be a segment of free RAM, where the tftp artifact
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# can be stored before unpacking it to the 'hardware.loadAddress'
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# The 'hardware.loadAddress' is 0x44000000, and the bootlog
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# suggests it loads the fit to 0x46000000
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loadAddress = lim.parseInt "0x46000000";
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};
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imageFormat = "fit";
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loader.fit.enable = lib.mkDefault true; # override this if you are building tftpboot
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};
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rootfsType = lib.mkDefault "ubifs"; # override this if you are building tftpboot
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filesystem =
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2025-02-10 21:55:08 +00:00
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let
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inherit (pkgs.pseudofile) dir symlink;
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in
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dir {
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lib = dir {
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firmware = dir {
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mediatek = symlink mediatek-firmware;
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airoha = symlink airoha-firmware;
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};
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};
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2024-12-18 13:17:46 +00:00
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};
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2025-02-10 21:55:08 +00:00
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hardware =
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let
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phy = pkgs.kmodloader.override {
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targets = [
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"air_en8811h"
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];
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inherit (config.system.outputs) kernel;
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};
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mac80211 = pkgs.kmodloader.override {
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targets = [
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"mt7915e"
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"rtc-pcf8563"
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"nvme_core"
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"nvme"
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#"mt7996e"
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"aquantia"
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];
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inherit (config.system.outputs) kernel;
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};
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in
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{
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# from OEM bootlog
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# Creating 4 MTD partitions on "spi0.0":
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# 0x000000000000-0x000000040000 : "bl2-nor"
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# 0x000000040000-0x000000100000 : "factory"
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# 0x000000100000-0x000000180000 : "fip-nor"
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# 0x000000180000-0x000000e00000 : "recovery"
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# spi-nand spi1.1: calibration result: 0x3
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# spi-nand spi1.1: Winbond SPI NAND was found.
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# spi-nand spi1.1: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
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# 2 fixed-partitions partitions found on MTD device spi1.1
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# Creating 2 MTD partitions on "spi1.1":
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# 0x000000000000-0x000000100000 : "bl2"
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# 0x000000100000-0x000010000000 : "ubi"
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flash = {
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# from the OEM bootlog:
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# ## Checking Image at 46000000 ...
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# FIT image found
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# FIT description: ARM64 OpenWrt FIT (Flattened Image Tree)
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# Image 0 (kernel-1)
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# Description: ARM64 OpenWrt Linux-6.6.57
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# Type: Kernel Image
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# Compression: gzip compressed
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# Data Start: 0x46001000
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# Data Size: 5751840 Bytes = 5.5 MiB
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# Architecture: AArch64
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# OS: Linux
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# Load Address: 0x44000000
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# Entry Point: 0x44000000
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address = lim.parseInt "0x44000000";
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size = lim.parseInt "0xf60000";
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# /proc/mtd on a running system:
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# dev: size erasesize name
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# mtd0: 00040000 00010000 "bl2-nor"
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# mtd1: 000c0000 00010000 "factory"
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# mtd2: 00080000 00010000 "fip-nor"
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# mtd3: 00c80000 00010000 "recovery"
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# mtd4: 00100000 00020000 "bl2"
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# mtd5: 0ff00000 00020000 "ubi"
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eraseBlockSize = 65536;
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};
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ubi = {
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# TODO taken from belkin-rt3200, to review
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minIOSize = "2048";
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logicalEraseBlockSize = "126976";
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physicalEraseBlockSize = "131072";
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maxLEBcount = "1024"; # guessing
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};
|
2024-12-18 13:17:46 +00:00
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|
2025-02-10 21:55:08 +00:00
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defaultOutput = "ubimage";
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loadAddress = lim.parseInt "0x44000000";
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entryPoint = lim.parseInt "0x44000000";
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|
|
# TODO AFAICT this should be 2048, but I got 'FIT: image rootfs-1 start not aligned to page boundaries' with that...
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#alignment = 2048;
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alignment = 4096;
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|
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rootDevice = "ubi0:liminix";
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dts = {
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src = "${openwrt.src}/target/linux/mediatek/dts/mt7981b-openwrt-one.dts";
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includePaths = [
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"${openwrt.src}/target/linux/mediatek/dts"
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"${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/"
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];
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};
|
2024-12-18 13:17:46 +00:00
|
|
|
|
2025-02-10 21:55:08 +00:00
|
|
|
networkInterfaces =
|
|
|
|
|
let
|
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|
|
inherit (config.system.service.network) link;
|
|
|
|
|
in
|
|
|
|
|
rec {
|
|
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|
|
eth0 = link.build {
|
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|
|
ifname = "eth0";
|
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|
|
dependencies = [ phy ];
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};
|
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|
|
eth1 = link.build { ifname = "eth1"; };
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wlan0 = link.build {
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|
|
ifname = "wlan0";
|
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|
|
dependencies = [ mac80211 ];
|
|
|
|
|
};
|
|
|
|
|
wlan1 = link.build {
|
|
|
|
|
ifname = "wlan1";
|
|
|
|
|
dependencies = [ mac80211 ];
|
|
|
|
|
};
|
2024-12-18 13:17:46 +00:00
|
|
|
};
|
2025-02-10 21:55:08 +00:00
|
|
|
};
|
|
|
|
|
};
|
2024-12-18 13:17:46 +00:00
|
|
|
};
|
|
|
|
|
}
|
