Add support for TP-Link Archer AX23
Arnout Engelen
parent
825528bc30
commit
60696dd8a2
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@ -0,0 +1,442 @@
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{
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description = ''
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TP-Link Archer AX23 / AX1800 Dual Band Wi-Fi 6 Router
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*****************************************************
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Hardware summary
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================
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- MediaTek MT7621 (880MHz)
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- 16MB Flash
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- 128MB RAM
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- WLan hardware: Mediatek MT7905, MT7975
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Limitations
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===========
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Status LEDs do not work yet.
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Uploading an image via tftp doesn't work yet, because the Archer uboot
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version is so old it doesn't support overriding the DTB from the mboot
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command. The tftpboot module doesn't support this yet, see
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https://gti.telent.net/dan/liminix/pulls/5 for the WiP.
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'';
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system = {
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crossSystem = {
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config = "mipsel-unknown-linux-musl";
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gcc = {
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abi = "32";
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# https://openwrt.org/docs/techref/instructionset/mipsel_24kc
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arch = "24kc";
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};
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};
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};
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module = {pkgs, config, lib, lim, ... }:
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let firmware = pkgs.stdenv.mkDerivation {
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name = "wlan-firmware";
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phases = ["installPhase"];
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installPhase = ''
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mkdir $out
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cp ${pkgs.linux-firmware}/lib/firmware/mediatek/{mt7915,mt7615,mt7622}* $out
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'';
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};
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in {
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imports = [
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../../modules/arch/mipsel.nix
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../../modules/outputs/tftpboot.nix
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../../modules/outputs/tplink.nix
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];
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config = {
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kernel = {
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src = pkgs.pkgsBuildBuild.fetchurl {
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name = "linux.tar.gz";
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url = "https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.15.137.tar.gz";
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hash = "sha256-PkdzUKZ0IpBiWe/RS70J76JKnBFzRblWcKlaIFNxnHQ=";
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};
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extraPatchPhase = ''
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${pkgs.openwrt.applyPatches.ramips}
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'';
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config = {
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# Initially taken from openwrt's ./target/linux/ramips/mt7621/config-5.15,
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# then tweaked here and there
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ARCH_32BIT_OFF_T="y";
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ARCH_HIBERNATION_POSSIBLE="y";
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ARCH_KEEP_MEMBLOCK="y";
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ARCH_MMAP_RND_BITS_MAX="15";
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ARCH_MMAP_RND_COMPAT_BITS_MAX="15";
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ARCH_SUSPEND_POSSIBLE="y";
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AT803X_PHY="y";
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BLK_MQ_PCI="y";
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BOARD_SCACHE="y";
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CEVT_R4K="y";
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CLKSRC_MIPS_GIC="y";
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CLK_MT7621="y";
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CLOCKSOURCE_WATCHDOG="y";
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CLONE_BACKWARDS="y";
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CMDLINE_BOOL="y";
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COMMON_CLK="y";
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COMPAT_32BIT_TIME="y";
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CPU_GENERIC_DUMP_TLB="y";
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CPU_HAS_DIEI="y";
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CPU_HAS_PREFETCH="y";
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CPU_HAS_RIXI="y";
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CPU_HAS_SYNC="y";
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CPU_LITTLE_ENDIAN="y";
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CPU_MIPS32="y";
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CPU_MIPS32_R2="y";
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CPU_MIPSR2="y";
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CPU_MIPSR2_IRQ_EI="y";
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CPU_MIPSR2_IRQ_VI="y";
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CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS="y";
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CPU_R4K_CACHE_TLB="y";
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CPU_RMAP="y";
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CPU_SUPPORTS_32BIT_KERNEL="y";
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CPU_SUPPORTS_HIGHMEM="y";
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CPU_SUPPORTS_MSA="y";
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CRC16="y";
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CRYPTO_DEFLATE="y";
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CRYPTO_HASH_INFO="y";
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CRYPTO_LIB_BLAKE2S_GENERIC="y";
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CRYPTO_LIB_POLY1305_RSIZE="2";
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CRYPTO_LZO="y";
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CRYPTO_ZSTD="y";
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CSRC_R4K="y";
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DIMLIB="y";
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DMA_NONCOHERENT="y";
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DTB_RT_NONE="y";
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DTC="y";
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EARLY_PRINTK="y";
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FIXED_PHY="y";
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FWNODE_MDIO="y";
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FW_LOADER_PAGED_BUF="y";
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GENERIC_ATOMIC64="y";
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GENERIC_CLOCKEVENTS="y";
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GENERIC_CMOS_UPDATE="y";
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GENERIC_CPU_AUTOPROBE="y";
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GENERIC_FIND_FIRST_BIT="y";
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GENERIC_GETTIMEOFDAY="y";
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GENERIC_IOMAP="y";
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GENERIC_IRQ_CHIP="y";
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GENERIC_IRQ_EFFECTIVE_AFF_MASK="y";
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GENERIC_IRQ_SHOW="y";
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GENERIC_LIB_ASHLDI3="y";
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GENERIC_LIB_ASHRDI3="y";
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GENERIC_LIB_CMPDI2="y";
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GENERIC_LIB_LSHRDI3="y";
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GENERIC_LIB_UCMPDI2="y";
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GENERIC_PCI_IOMAP="y";
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GENERIC_PHY="y";
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GENERIC_PINCONF="y";
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GENERIC_SCHED_CLOCK="y";
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GENERIC_SMP_IDLE_THREAD="y";
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GENERIC_TIME_VSYSCALL="y";
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GLOB="y";
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GPIOLIB_IRQCHIP="y";
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GPIO_CDEV="y";
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GPIO_GENERIC="y";
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GPIO_MT7621="y";
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GRO_CELLS="y";
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HANDLE_DOMAIN_IRQ="y";
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HARDWARE_WATCHPOINTS="y";
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HAS_DMA="y";
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HAS_IOMEM="y";
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HAS_IOPORT_MAP="y";
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I2C="y";
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I2C_ALGOBIT="y";
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I2C_BOARDINFO="y";
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I2C_CHARDEV="y";
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I2C_GPIO="y";
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I2C_MT7621="y";
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ICPLUS_PHY="y";
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IRQCHIP="y";
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IRQ_DOMAIN="y";
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IRQ_DOMAIN_HIERARCHY="y";
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IRQ_FORCED_THREADING="y";
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IRQ_MIPS_CPU="y";
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IRQ_WORK="y";
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LIBFDT="y";
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LOCK_DEBUGGING_SUPPORT="y";
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LZO_COMPRESS="y";
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LZO_DECOMPRESS="y";
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MDIO_BUS="y";
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MDIO_DEVICE="y";
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MDIO_DEVRES="y";
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MEDIATEK_GE_PHY="y";
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MEMFD_CREATE="y";
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MFD_SYSCON="y";
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MIGRATION="y";
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MIKROTIK="y";
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MIKROTIK_RB_SYSFS="y";
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MIPS="y";
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MIPS_ASID_BITS="8";
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MIPS_ASID_SHIFT="0";
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MIPS_CLOCK_VSYSCALL="y";
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MIPS_CM="y";
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MIPS_CPC="y";
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MIPS_CPS="y";
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MIPS_CPU_SCACHE="y";
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MIPS_GIC="y";
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MIPS_L1_CACHE_SHIFT="5";
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MIPS_LD_CAN_LINK_VDSO="y";
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MIPS_MT="y";
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MIPS_MT_FPAFF="y";
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MIPS_MT_SMP="y";
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MIPS_NR_CPU_NR_MAP="4";
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MIPS_PERF_SHARED_TC_COUNTERS="y";
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MIPS_SPRAM="y";
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MODULES_USE_ELF_REL="y";
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MTD_CMDLINE_PARTS="y";
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MTD_NAND_CORE="y";
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MTD_NAND_ECC="y";
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MTD_NAND_ECC_SW_HAMMING="y";
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MTD_NAND_MT7621="y";
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MTD_NAND_MTK_BMT="y";
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MTD_RAW_NAND="y";
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MTD_ROUTERBOOT_PARTS="y";
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MTD_SERCOMM_PARTS="y";
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MTD_SPI_NOR="y";
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MTD_SPLIT_FIT_FW="y";
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MTD_SPLIT_MINOR_FW="y";
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MTD_SPLIT_SEAMA_FW="y";
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MTD_SPLIT_TPLINK_FW="y";
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MTD_SPLIT_TRX_FW="y";
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MTD_SPLIT_UIMAGE_FW="y";
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MTD_UBI="y";
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MTD_UBI_BEB_LIMIT="20";
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MTD_UBI_BLOCK="y";
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MTD_UBI_WL_THRESHOLD="4096";
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MTD_VIRT_CONCAT="y";
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NEED_DMA_MAP_STATE="y";
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NET_DEVLINK="y";
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NET_DSA="y";
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NET_DSA_MT7530="y";
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NET_DSA_MT7530_MDIO="y";
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NET_DSA_TAG_MTK="y";
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NET_FLOW_LIMIT="y";
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NET_MEDIATEK_SOC="y";
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NET_SELFTESTS="y";
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NET_SWITCHDEV="y";
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NET_VENDOR_MEDIATEK="y";
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NO_HZ_COMMON="y";
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NO_HZ_IDLE="y";
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NR_CPUS="4";
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NVMEM="y";
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OF="y";
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OF_ADDRESS="y";
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OF_EARLY_FLATTREE="y";
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OF_FLATTREE="y";
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OF_GPIO="y";
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OF_IRQ="y";
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OF_KOBJ="y";
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OF_MDIO="y";
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PAGE_POOL="y";
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PAGE_POOL_STATS="y";
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PCI="y";
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PCIE_MT7621="y";
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PCI_DISABLE_COMMON_QUIRKS="y";
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PCI_DOMAINS="y";
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PCI_DOMAINS_GENERIC="y";
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PCI_DRIVERS_GENERIC="y";
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PCS_MTK_LYNXI="y";
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PERF_USE_VMALLOC="y";
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PGTABLE_LEVELS="2";
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PHYLIB="y";
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PHYLINK="y";
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PHY_MT7621_PCI="y";
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PINCTRL="y";
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PINCTRL_AW9523="y";
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PINCTRL_MT7621="y";
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PINCTRL_RALINK="y";
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PINCTRL_SX150X="y";
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POWER_RESET="y";
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POWER_RESET_GPIO="y";
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POWER_SUPPLY="y";
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PTP_1588_CLOCK_OPTIONAL="y";
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QUEUED_RWLOCKS="y";
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QUEUED_SPINLOCKS="y";
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RALINK="y";
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RATIONAL="y";
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REGMAP="y";
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REGMAP_I2C="y";
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REGMAP_MMIO="y";
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REGULATOR="y";
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REGULATOR_FIXED_VOLTAGE="y";
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RESET_CONTROLLER="y";
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RFS_ACCEL="y";
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RPS="y";
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RTC_CLASS="y";
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RTC_DRV_BQ32K="y";
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RTC_DRV_PCF8563="y";
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RTC_I2C_AND_SPI="y";
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SCHED_SMT="y";
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SERIAL_8250="y";
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SERIAL_8250_CONSOLE="y";
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SERIAL_8250_NR_UARTS="3";
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SERIAL_8250_RUNTIME_UARTS="3";
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SERIAL_MCTRL_GPIO="y";
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SERIAL_OF_PLATFORM="y";
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SGL_ALLOC="y";
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SMP="y";
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SMP_UP="y";
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SOCK_RX_QUEUE_MAPPING="y";
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SOC_BUS="y";
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SOC_MT7621="y";
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SPI="y";
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SPI_MASTER="y";
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SPI_MEM="y";
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SPI_MT7621="y";
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SRCU="y";
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SWPHY="y";
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SYNC_R4K="y";
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SYSCTL_EXCEPTION_TRACE="y";
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SYS_HAS_CPU_MIPS32_R1="y";
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SYS_HAS_CPU_MIPS32_R2="y";
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SYS_HAS_EARLY_PRINTK="y";
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SYS_SUPPORTS_32BIT_KERNEL="y";
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SYS_SUPPORTS_ARBIT_HZ="y";
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SYS_SUPPORTS_HIGHMEM="y";
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SYS_SUPPORTS_HOTPLUG_CPU="y";
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SYS_SUPPORTS_LITTLE_ENDIAN="y";
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SYS_SUPPORTS_MIPS16="y";
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SYS_SUPPORTS_MIPS_CPS="y";
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SYS_SUPPORTS_MULTITHREADING="y";
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SYS_SUPPORTS_SCHED_SMT="y";
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SYS_SUPPORTS_SMP="y";
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SYS_SUPPORTS_ZBOOT="y";
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TARGET_ISA_REV="2";
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TICK_CPU_ACCOUNTING="y";
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TIMER_OF="y";
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TIMER_PROBE="y";
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TREE_RCU="y";
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TREE_SRCU="y";
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UBIFS_FS="y";
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USB_SUPPORT="y";
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USE_OF="y";
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WEAK_ORDERING="y";
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XPS="y";
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XXHASH="y";
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ZLIB_DEFLATE="y";
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ZLIB_INFLATE="y";
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ZSTD_COMPRESS="y";
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ZSTD_DECOMPRESS="y";
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} // lib.optionalAttrs (config.system.service ? watchdog) {
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RALINK_WDT = "y"; # watchdog
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MT7621_WDT = "y"; # or it might be this one
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};
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};
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tplink.board = "ARCHER-AX23-V1";
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boot = {
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commandLine = [ "console=ttyS0,115200" ];
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tftp = {
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# IP addresses to use in the boot monitor when flashing/ booting
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# over TFTP. If you are flashing using the stock firmware's Web UI
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# then these dummy values are fine
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ipaddr = "192.168.0.1"; # router address
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serverip = "192.168.0.5"; # build machine or other tftp server
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# Should be a segment of free RAM, where the tftp artifact
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# can be stored before unpacking it to the 'hardware.loadAddress'
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# The 'hardware.loadAddress' is 0x80001000, which suggests the
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# RAM would start at 0x8000000 and (being 128MB) go to
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# to 0x8800000. Let's put it at the 100MB mark at
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# 0x8000000+0x0640000=0x86400000
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loadAddress = lim.parseInt "0x86400000";
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};
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};
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filesystem =
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let inherit (pkgs.pseudofile) dir symlink;
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in
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dir {
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lib = dir {
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firmware = dir {
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mediatek = symlink firmware;
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};
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};
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};
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hardware =
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let
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openwrt = pkgs.openwrt;
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mac80211 = pkgs.mac80211.override {
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drivers = [
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"mt7915e"
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];
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klibBuild = config.system.outputs.kernel.modulesupport;
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};
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in {
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# from OEM bootlog (openwrt wiki):
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# 4 cmdlinepart partitions found on MTD device raspi
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# Creating 4 MTD partitions on "raspi":
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# 0x000000000000-0x000000040000 : "uboot"
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# 0x000000040000-0x000000440000 : "uImage"
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# 0x000000440000-0x000000ff0000 : "rootfs"
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# 0x000000ff0000-0x000001000000 : "ART"
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# from openwrt bootlog (openwrt wiki):
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# 5 fixed-partitions partitions found on MTD device spi0.0
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# OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
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# OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
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# OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
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# OF: Bad cell count for /palmbus@1e000000/spi@b00/flash@0/partitions
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# Creating 5 MTD partitions on "spi0.0":
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# 0x000000000000-0x000000040000 : "u-boot"
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# 0x000000040000-0x000000fa0000 : "firmware"
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# 2 uimage-fw partitions found on MTD device firmware
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# Creating 2 MTD partitions on "firmware":
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# 0x000000000000-0x0000002c0000 : "kernel"
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# 0x0000002c0000-0x000000f60000 : "rootfs"
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# mtd: setting mtd3 (rootfs) as root device
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# 1 squashfs-split partitions found on MTD device rootfs
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# 0x000000640000-0x000000f60000 : "rootfs_data"
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# 0x000000fa0000-0x000000fb0000 : "config"
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# 0x000000fb0000-0x000000ff0000 : "tplink"
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# 0x000000ff0000-0x000001000000 : "radio"
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flash = {
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# from the OEM bootlog 'Booting image at bc040000'
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# (0x40000 from 0xbc000000)
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address = lim.parseInt "0xbc040000";
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# 0x000000040000-0x000000fa0000
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size = lim.parseInt "0xf60000";
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# guessed:
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eraseBlockSize = 65536;
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};
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# since this is mentioned in the partition table as well?
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defaultOutput = "tplink";
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# taken from openwrt sysupgrade image:
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# openwrt-23.05.2-ramips-mt7621-tplink_archer-ax23-v1-squashfs-sysupgrade.bin: u-boot legacy uImage, MIPS OpenWrt Linux-5.15.137, Linux/MIPS, OS Kernel Image (lzma), 2797386 bytes, Tue Nov 14 13:38:11 2023, Load Address: 0X80001000, Entry Point: 0X80001000, Header CRC: 0X19F74C5B, Data CRC: 0XF685563C
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loadAddress = lim.parseInt "0x80001000";
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entryPoint = lim.parseInt "0x80001000";
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rootDevice = "/dev/mtdblock3";
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dts = {
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src = "${openwrt.src}/target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts";
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includes = [
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"${openwrt.src}/target/linux/ramips/dts"
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"${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/"
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];
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};
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networkInterfaces =
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let
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inherit (config.system.service.network) link;
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inherit (config.system.service) bridge;
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in rec {
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lan1 = link.build { ifname = "lan1"; };
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lan2 = link.build { ifname = "lan2"; };
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lan3 = link.build { ifname = "lan3"; };
|
||||
lan4 = link.build { ifname = "lan4"; };
|
||||
wan = link.build { ifname = "wan"; };
|
||||
|
||||
wlan = link.build {
|
||||
ifname = "wlan0";
|
||||
dependencies = [ mac80211 ];
|
||||
};
|
||||
wlan5 = link.build {
|
||||
ifname = "wlan1";
|
||||
dependencies = [ mac80211 ];
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
}
|
||||
Loading…
Reference in New Issue